CS4265 Datasheet, PDF (35/53 Pages) Cirrus Logic – 105 dB, 24-Bit, 192 kHz Stereo Audio CODEC

CS4265
Gain
dB
0dB
T1=50 µs
-10dB
T2 = 15 µs
F1
3.183 kHz
F2 Frequency
10.61 kHz
Figure 17. De-Emphasis Curve
6.4.1 Functional Mode (Bits 7:6)
Function:
Selects the required range of sample rates.
Table 7. Functional Mode Selection
FM1
0
0
1
1
FM0
0
1
0
1
Mode
Single-Speed Mode: 4 to 50 kHz sample rates
Double-Speed Mode: 50 to 100 kHz sample rates
Quad-Speed Mode: 100 to 200 kHz sample rates
Reserved
6.4.2 ADC Digital Interface Format (Bit 4)
Function:
The required relationship between LRCK, SCLK and SDOUT is defined by the ADC Digital Interface
Format bit. The options are detailed in Table 8 and may be seen in Figure 5 and 6.
Table 8. ADC Digital Interface Formats
6.4.3
ADC_DIF
Description
0
Left Justified, up to 24-bit data (default)
1
I²S, up to 24-bit data
Mute ADC (Bit 2)
Format
0
1
Figure
5
6
Function:
When this bit is set, the serial audio output of the both ADC channels will be muted.
6.4.4 ADC High Pass Filter Freeze (Bit 1)
Function:
When this bit is set, the internal high-pass filter will be disabled.The current DC offset value will be
frozen and continue to be subtracted from the conversion result. See “High Pass Filter and DC Offset
Calibration” on page 23.
DS657A2
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