CS4265 Datasheet, PDF (34/53 Pages) Cirrus Logic – 105 dB, 24-Bit, 192 kHz Stereo Audio CODEC

CS4265
The device will enter a low-power state whenever this bit is set. The power-down bit is set by default
and must be cleared before normal operation can occur. The contents of the control registers are re-
tained when the device is in power-down.
6.3 DAC Control - Address 03h
7
Reserved
6
Reserved
5
DAC_DIF1
4
DAC_DIF0
3
Reserved
2
MuteDAC
1
DeEmph
0
Reserved
6.3.1 DAC Digital Interface Format (Bits 5:4)
Function:
The required relationship between LRCK, SCLK and SDIN for the DAC is defined by the DAC Digital
Interface Format and the options are detailed in Table 5 and Figures 5-7.
Table 5. DAC Digital Interface Formats
6.3.2
DAC_DIF1 DAC_DIF0
0
0
0
1
1
0
1
1
Mute DAC (Bit 2)
Description
Left Justified, up to 24-bit data (default)
I²S, up to 24-bit data
Right Justified, 16-bit Data
Right Justified, 24-bit Data
Format
0
1
2
3
Figure
5
6
7
7
Function:
The DAC outputs will mute and the MUTEC pin will become active when this bit is set. Though this
bit is active high, it should be noted that the MUTEC pin is active low. The common mode voltage on
the outputs will be retained when this bit is set. The muting function is effected, similar to attenuation
changes, by the DACSoft and DACZero bits in the DAC Control 2 register.
6.3.3 De-Emphasis Control (Bit 1)
Function:
The standard 50/15 µs digital de-emphasis filter response, Figure 17, may be implemented for a sam-
ple rate of 44.1 kHz when the DeEmph bit is configured as shown in Table 6 below. NOTE: De-em-
phasis is available only in Single-Speed Mode.
Table 6. De-Emphasis Control
DeEmph
0
1
Description
Disabled (default)
44.1 kHz de-emphasis
6.4 ADC Control - Address 04h
7
FM1
6
FM0
5
4
3
2
1
0
Reserved
ADC_DIF
Reserved
MuteADC HPFFreeze
M/S
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DS657A2