HCPL-7710-000E Datasheet, PDF (8/18 Pages) AVAGO TECHNOLOGIES LIMITED – 40 ns Propagation Delay, CMOS Optocoupler

Package Characteristics
Parameter
Symbol Min. Typ. Max. Units Test Conditions
Input-Output Momentary
Withstand Voltage ^{[8, 9, 10]}
0710
7710
Option 020
V_ISO 3750
3750
5000
Vrms
RH = 50%,
t = 1 min.,
T_A = 25°C
Resistance
(Input-Output) ^[8]
R_I-O
10¹²
W
V_I-O = 500 Vdc
Capacitance
(Input-Output) ^[8]
C_I-O
0.6
pF f = 1 MHz
Input Capacitance ^[11]
C_I
Input IC Junction-to-Case
-7710
q_jci
Thermal Resistance
-0710
Output IC Junction-to-Case -7710
q_jco
Thermal Resistance
-0710
3.0
145
°C/W Thermocouple
160
located at center
underside of package
140
135
Package Power Dissipation
P_PD
150 mW
Notes:
  1. The LED is ON when V_I is low and OFF when V_I is high.
  2. t_PHL propagation delay is measured from the 50% level on the falling edge of the V_I signal to the 50% level of the falling edge of the V_O signal.
t_PLH propagation delay is measured from the 50% level on the rising edge of the V_I signal to the 50% level of the rising edge of the V_O signal.
  3. Mimimum Pulse Width is the shortest pulse width at which 10% maximum, Pulse Width Distortion can be guaran­teed. Maximum Data Rate is
the inverse of Minimum Pulse Width. Operating the HCPL-x710 at data rates above 12.5 MBd is possible provided PWD and data dependent
jitter increases and relaxed noise margins are tolerable within the application. For instance, if the maximum allowable variation of bit width is
30%, the maximum data rate becomes 37.5 MBd. Please note that HCPL-x710 performances above 12.5 MBd are not guaranteed by Hewlett-
Packard.
  4. PWD is defined as |t_PHL - t_PLH|. %PWD (percent pulse width distortion) is equal to the PWD divided by pulse width.
  5. t_PSK is equal to the magnitude of the worst case difference in t_PHL and/or t_PLH that will be seen between units at any given temperature within
the recommended operating conditions.
  6. CM_H is the maximum common mode voltage slew rate that can be sustained while maintaining V_O > 0.8 V_DD2. CM_L is the maximum common
mode voltage slew rate that can be sustained while maintaining V_O < 0.8 V. The common mode voltage slew rates apply to both rising and
falling common mode voltage edges.
  7. Unloaded dynamic power dissipation is calculated as follows: C_PD * V_DD2 * f + I_DD * V_DD, where f is switching frequency in MHz.
8. Device considered a two-terminal device: pins 1, 2, 3, and 4 shorted together and pins 5, 6, 7, and 8 shorted together.
9. In accordance with UL1577, each HCPL-0710 is proof tested by applying an insulation test voltage ≥4500 V_RMS for 1 second (leakage detec-
tion current limit, I_I-O ≤5 µA). Each HCPL-7710 is proof tested by applying an insulation test voltage ≥ 4500 V rms for 1 second (leakage detec-
tion current limit, I_I-O ≤ 5 µA).
10. The Input-Output Momentary With­stand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous
voltage rating. For the continuous voltage rating refer to your equipment level safety specification or Avago Application Note 1074 entitled
“Optocoupler Input-Output Endurance Voltage.”
11. C_I is the capacitance measured at pin 2 (V_I).
5
0 °C
4
25 °C
85 °C
3
2
1
0
0
1
2
3
V_I (V)
4
5
Figure 1. Typical output voltage vs. input voltage.
HCPL-0710 fig 1

2.2
0 °C
2.1
25 °C
85 °C
2.0
1.9
1.8
1.7
1.6
4.5
4.75
5
5.25
5.5
V_DD1 (V)
Figure 2. Typical input voltage switching threshold vs.
input supply voltage.
HCPL-0710 fig 2
29
27
25
T_PLH
23
21
T_PHL
19
17
15
0 10 20 30 40 50 60 70 80
T_A (C)
Figure 3. Typical propagation delays vs. temperature.
HCPL-0710 fig 3