HCPL-7710-000E Datasheet, PDF (1/18 Pages) AVAGO TECHNOLOGIES LIMITED – 40 ns Propagation Delay, CMOS Optocoupler

HCPL-7710/0710
40 ns Propagation Delay, CMOS Optocoupler
Data Sheet
Lead (Pb) Free
RoHS 6 fully
compliant
RoHS 6 fully compliant options available;
-xxxE denotes a lead-free product
Description
Features
Available in either an 8-pin DIP or SO-8 package style
respectively, the HCPL-7710 or HCPL-0710 optocouplers
utilize the latest CMOS IC technology to achieve outstand-
ing performance with very low power consumption. The
HCPL-x710 require only two bypass capacitors for complete
CMOS compatibility.
• +5 V CMOS compatibility
• 8 ns maximum pulse width distortion
• 20 ns maximum prop. delay skew
• High speed: 12 Mbd
• 40 ns maximum prop. delay
Basic building blocks of the HCPL-x710 are a CMOS LED
driver IC, a high speed LED and a CMOS detector IC. A
CMOS logic input signal controls the LED driver IC which
supplies current to the LED. The detector IC incorporates
an integrated photodiode, a high-speed transimped-
ance amplifier, and a voltage comparator with an output
driver.
• 10 kV/µs minimum common mode rejection
• -40°C to 100°C temperature range
• Safety and regulatory approvals
UL Recognized
3750 V rms for 1 min. per UL 1577
5000 V rms for 1 min. per UL 1577 (for HCPL-7710
option 020)
CSA Component Acceptance Notice #5
Functional Diagram
IEC/EN/DIN EN 60747-5-2
**V_DD1 1
8 V_DD2**
TRUTH^{– V}TAIOBRMLE^{= 630 Vpeak for HCPL-7710 Option 060}
(POSITI_–VE_VIL_OO_RMGI₌C)_{560 Vpeak for HCPL-0710 Option 060}
V_I, INPUT LED1 V_O, OUTPUT
V_I 2
7 NC*
H
L
App^OOli^Fc_NFations
H
L
• Digital fieldbus isolation: DeviceNet, SDS, Profibus
NC* 3
GND₁ 4
LED1
SHIELD
I_O
6 V_O
5 GND₂
• AC plasma display panel level shifting
• Multiplexed data transmission
• Computer peripheral interface
• Microprocessor system interface
* Pin 3 is the anode of the internal LED and must be left
unconnected for guaranteed data sheet performance.
Pin 7 is not connected internally.
** A 0.1 µF bypass capacitor must be connected
between pins 1 and 4, and 5 and 8.
8 V_DD2**
7 NC*
TRUTH TABLE
(POSITIVE LOGIC)
V_I, INPUT
H
L
LED1
OFF
ON
V_O, OUTPUT
H
L
I_O
6 V_O
CAUTION: It is advised that normal static precautions be taken in handling and assembly
of this component to prevent damage and/or degradation which may be induced by ESD.
5 GND₂