HCPL-7710-000E Datasheet, PDF (7/18 Pages) AVAGO TECHNOLOGIES LIMITED – 40 ns Propagation Delay, CMOS Optocoupler

Electrical Specifications
Test conditions that are not specified can be anywhere within the recommended operating range.
All typical specifications are at T_A = +25°C, V_DD1 = V_DD2 = +5 V.
DC Specifications
Parameter
Symbol
Min.
Typ. Max. Units
Logic Low Input
Supply Current ^[1]
I_DD1L
6.0 10.0 mA
Logic High Input
Supply Current
I_DD1H
1.5 3.0 mA
Input Supply Current
I_DD1
13.0 mA
Output Supply Current
I_DD2
5.5 11.0 mA
Input Current
I_I
-10
10
µA
Logic High Output
V_OH
Voltage
4.4
5.0
V
4.0
4.8
Logic Low Output
V_OL
Voltage
0
0.1 V
0.5 1.0
Test Conditions
V_I = 0 V
V_I = V_DDI
I_O = -20 µA, V_I = V_IH
I_O = -4 mA, V_I = V_IH
I_O = -20 µA, V_I = V_IL
I_O = -4 mA, V_I = V_IL
Switching Specifications
Parameter
Symbol
Min.
Typ. Max. Units
Propagation Delay Time
t_PHL
20
40
ns
to Logic Low Output ^[2]
Propagation Delay Time
t_PHL
20
40
ns
to Logic Low Output ^[2]
Propagation Delay Time
t_PLH
23
40
ns
to Logic High Output
Pulse Width ^[3]
PW
80
ns

Data Rate ^[3]
12.5 MBd

Pulse Width Distortion ^[4]
PWD
3
8
ns
|t_PHL - t_PLH|
Propagation Delay Skew ^[5]
t_PSK
20 ns
Output Rise Time
t_R
9
ns
(10 - 90%)
Output Fall Time
t_F
8
ns
(90 - 10%)
Common Mode
|CM_H|
10
20
kV/µs
Transient Immunity at
Logic High Output ^[6]
Common Mode
|CM_L|
10
20
kV/µs
Transient Immunity at
Logic Low Output ^[6]
Input Dynamic Power
Dissipation Capacitance ^[7]
C_PD1
60
pF
Output Dynamic Power
Dissipation Capacitance ^[7]
C_PD2
10
pF
Test Conditions
C_L = 15 pF
CMOS Signal Levels
C_L = 15 pF
CMOS Signal Levels
C_L = 15 pF
CMOS Signal Levels
C_L = 15 pF
CMOS Signal Levels
C_L = 15 pF
CMOS Signal Levels
C_L = 15 pF
CMOS Signal Levels
C_L = 15 pF
C_L = 15 pF
CMOS Signal Levels
C_L = 15 pF
CMOS Signal Levels
V_I = V_DD1, V_O >
0.8 V_DD1,
V_CM = 1000 V
V_I = 0 V, V_O > 0.8 V,
V_CM = 1000 V