HCPL-7710-000E Datasheet, PDF (10/18 Pages) AVAGO TECHNOLOGIES LIMITED – 40 ns Propagation Delay, CMOS Optocoupler

Application Information
Bypassing and PC Board Layout
The HCPL-x710 optocouplers are extremely easy to
use. No external interface circuitry is required because
the HCPL-x710 use high-speed CMOS IC technology
allowing CMOS logic to be connected directly to the
inputs and outputs.
As shown in Figure 12, the only external components
required for proper operation are two bypass capacitors.
Capacitor values should be between 0.01 µF and 0.1 µF.
For each capacitor, the total lead length between both
ends of the capacitor and the power-supply pins should
not exceed 20 mm. Figure 13 illustrates the recommend-
ed printed circuit board layout for the HPCL-x710.
V_DD1
1
C1
V_I
2
NC 3
GND₁
4
8
C2
7 NC
V_DD2
6
V_O
5
GND₂
C1, C2 = 0.01 µF TO 0.1 µF
Figure 12. Recommended Printed Circuit Board layout.
V_DD1
V_I
C1
GND₁
HCPL-0710 fig 11
Figure 13. Recommended Printed Circuit Board layout.
V_DD2
C2
V_O
GND₂
C1, C2 = 0.01 µF TO 0.1 µF
Propagation Delay, Pulse-Width Distortion and Propagation Delay
Skew
Propagation Delay is a figure of merit w_Hh_Ci_Pc_Lh_-0d₇₁e₀s_fc_igrib₁₂es
how quickly a logic signal propagates through a
system. The propaga­tion delay from low to high (t_PLH)
is the amount of time required for an input signal to
propagate to the output, causing the output to change
from low to high. Similarly, the propagation delay from
high to low (t_PHL) is the amount of time required for the
input signal to propagate to the output, causing the
output to change from high to low. See Figure 14.
INPUT
V_I
OUTPUT
V_O
10%
t_PLH
90%
Figure 14.
t_PHL
50%
90%
10%
5 V CMOS
0V
V_OH
2.5 V CMOS
V_OL
10
HCPL-0710 fig 13