HCTL-1101 Datasheet, PDF (6/40 Pages) AVAGO TECHNOLOGIES LIMITED – General Purpose Control ICs Position and Velocity Control Low Power CMOS

AC Electrical Characteristics
VDD = 5V + 5%; TA = -200C to +850C; Units + nsec
ID # Signal
1 Clock Period (clk)
2 Pulse Width, Clock High
3 Pulse Width, Clock Low
4 Clock Rise and Fall Time
5 Input Pulse Width RESET
6 Input Pulse Width STOP, LIMIT
Symbol
t_CPER
t_CPWH
t_CPWL
t_CR
t_IRST
t_IP
Clock Frequency
2 MHz
Min. Max.
500
230
200
20
2500
600
1 MHz
Min. Max.
1000
300
200
20
5000
1100
7 Input Pulse Width INDEX
t_IX
1600
3100
8 Input Pulse Width CHA, CHB
t_IAB
1600
3100
9 Delay CHA to CHB Transition
t_AB
600
1100
10 Input Rise/Fall Time
t_IABR
(CHA, CHB, INDEX)
11 Input Rise/Fall Time RESET, ALE, CS, OE,
t_IR
STOP, LIMIT
12 Input Pulse Width ALE, CS
t_IPW
13 Delay Time, ALE Rise to CS Rise
14 Address Setup Time Before
ALE Fall/Rise
t_CA
t_ASR1
15 Address Setup Time Before
t_ASR
CS Fall/Rise
16 Write Data Setup Time Before CS Rise
t_DSR
17 Address/Data Hold Time
t_H
18 Setup Time, R/W Before CS Rise
t_WCS
19 Hold Time, R/W After CS Rise
t_WH
20 Delay Time, Write Cycle, CS Rise to ALE Fall t_CSAL
21 Delay Time, Read/Write, CS Rise to CS Fall
22 Write Cycle, ALE Fall to ALE Fall
For Next Write
t_CSCS
t_WC
23 Delay Time, CS Rise to OE Fall
t_CSOE
150
20
80
50
20
20
20
20
20
20
1700
1500
1850
1700
300
20
80
50
20
20
20
20
20
20
3400
3000
3700
3200
24 Delay Time, OE Fall to Data Bus Valid
t_OEDB
25 Input Pulse Width OE
t_IPWOE
26 Hold Time, Data Held After OE Rise
t_DOEH
27 Delay Time, Read Cycle, CS Rise to ALE Fall t_CSALR
100
100
20
1820
100
100
20
3320
28 Read Cycle, ALE Fall to ALE Fall
t_RC
For Next Read
29 Output Pulse Width, PROF, INIT, Pulse, Sign, t_OF
PHA-PHD, MC Port
30 Output Rise/Fall Time, PROF, INIT, Pulse, Sign, t_OR
PHA-PHD, MC Port
31 Delay Time, Clock Rise to Output Rise
t_EP
(PROF,INIT,PULSE,SIGN,PHASE)
32 Pulse Width, SYNC Low
t_SYNC
1950
500
10
100
300
9000
3450
1000
20
150
300
18000
Note:
*General formula for determining AC characteristics for other clock frequencies (clk), between 100 kHz and 2 MHz.
Formula*
Min.
Max.
200
5 clk
1 clk
+ 100 ns
3 clk
+ 100 ns
3 cl
+ 100 ns
1 clk
+ 100 ns
20
300(clk <
1 MHz)
20
80
50
20
20
20
20
20
20
3.4 clk
3 clk
3.7 clk
3 clk
+ 200 ns
100
100
20
3 clk
+ 320 ns
3 clk
+ 450 ns
1 clk
10
150
300
18 clk
6