HCTL-1101 Datasheet, PDF (37/40 Pages) AVAGO TECHNOLOGIES LIMITED – General Purpose Control ICs Position and Velocity Control Low Power CMOS

Applications of the HCTL-1101
Interfacing the HCTL-1101 to Host Processors
The HCTL-1101 looks to the host microprocessor like a
bank of 8-bit registers to which the host processor can
read and write (i.e., the host processor treats the HCTL-
1101 like RAM). The data in these registers controls the
operation of the HCTL-1101. The host processor commu-
nicates to the HCTL-1101 over a bidirectional multiplexed
8-bit data bus. The four I/O control lines. ALE, CS, OE, and
R/W execute the data transfer (see Figure 15).
There are three different timing configuration which can be
used to give the user greater flexibility to interface HCTL-
1101 to most microprocessors (see timing diagrams). They
are differentiated from one another by the arrangement
of the ALE signal with respect to the CS signal. The three
timing configuration are listed below:
37
• ALE, CS non-overlapped
• ALE, CS overlapped
• ALE within CS
Any I/O operation starts by asserting the ALE signal which
starts sampling the external bus into an internal address
latch. Rising ALE or falling CS during ALE stops the sam-
pling into the address latch.
CS low after rising ALE samples the external bus into the
data latch. Rising CS stops the sampling into the data
latch, and starts the internal synchronous process.
In the case of a write, the data in the data latch is written
into the addressed location. In the case of a read, the ad-
dressed location is written into an internal output latch.