HCTL-1101 Datasheet, PDF (11/40 Pages) AVAGO TECHNOLOGIES LIMITED – General Purpose Control ICs Position and Velocity Control Low Power CMOS

Pin Descriptions and Functions
Input/Output Pins
Pin Number
Symbol PDIP PLCC
AD0/DB00- 2-7
3-8
AD5/DB5
DB6, DB7 8, 9
9, 10
Description
Address/Data Bus – Lower 6 bits of 8-bit I/O port which are multiplexed between address and
data.
Data bus – Upper 2 bits of 8-bit I/O port used for data only.
Input Signals
Symbol
CHA/CHB
Pin Number
PDIP PLCC
31, 30 34, 33
INDEX
33
36
R/W
37
41
ALE
38
42
CS
39
43
OE
40
44
LIMIT
14
15
STOP
RESET
ExtClk
V_DD
GND
SYNC
NC
15
16
36
34
11, 35
10, 32
1
–
40
37
12, 38
1, 11,
23, 35
2
17, 39
Description
Channel A, B – Input pins for position feedback from an incremental shaft encoder.
Two channels, A and B, 90 degrees out of phase are required.
INDEX Pulse – Input from the reference or INDEX pulse of an incremental encoder.
Used only in conjunction with the Commutator. Either a low or high true signal can be used with
the INDEX pin. See Timing Diagrams and Encoder Interface section for more detail.
Read/Write – Determines direction of data exchange for the I/O port.
Address Latch Enable – Enables lower 6 bits of external data bus into internal address latch.
Chip Select – Performs I/O operation dependent on status of R/W line. For a Write, the external
bus data is written into the internal addressed location. For Read, data is read from an internal
location into an internal output latch.
Output Enable – Enables the data in the internal output latch onto the external data bus to
complete a Read operation.
LIMIT Switch – An internal flag which when externally set, triggers an unconditional branch to
the Initialization/Idle mode before the next control sample is executed. Motor Command is set to
zero. Status of the LIMIT flag is monitored in the Status register.
STOP Flag – An internal flag that is externally set. When flag is set during Integral Velocity
Control mode, the Motor Command is decelerated to a stop.
RESET – A hard reset of internal circuitry and a branch to Reset mode.
External Clock
Voltage Supply – Both V_DD pins must be connected to a 5.0 volt supply.
Circuit Ground
Used to synchronize multiple HCTL-1101 sample timers.
Not connected. These pins should be left floating.
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