HCTL-1101 Datasheet, PDF (22/40 Pages) AVAGO TECHNOLOGIES LIMITED – General Purpose Control ICs Position and Velocity Control Low Power CMOS

Figure 5. PWM Port Output.
Figure 6. Sign Reversal Inhibit.
Actual Position Registers
Read, Clear
: R12H, R13H, R14H
Preset
: R15H, R16H, and R17H
The Actual Position Register is accessed by two sets of reg-
isters in the HCTL-1101. When reading the Actual Position
from the HCTL-1101, the host processor will read Registers
R12H (MSB), R13H, and R14H (LSB). When presetting the
Actual Position Register, the processor will write to Regis-
ters R15H (MSB), R16H, and R17H (LSB).
When reading the Actual Position registers, the order
should be R14H, R13H, and R12H. These registers are
latched, such that, when reading Register R14H, all three
bytes will be latched so that count data does not change
while reading three separate bytes.
When presetting the Actual Position Register, write to
R15H and R16H first. When R17H is written to, all three
bytes are simultaneously loaded into the Actual Position
Register.
Note that presetting the Actual Position Registers is only
allowed while the HCTL-1101 is in INIT/ IDLE mode.
The Actual Position Registers can be simultaneously
cleared at any time by writing any value to R13H.
22
Digital Filter Registers
Zero (A) R20H
Pole (B) R21H
Gain (K) R22H
All control modes use some part of the programmable
digital filter D (z) to compensate for closed loop system
stability. The compensation D (z) has the form:
Where:
z = the digital domain operator
K = digital filter gain (R22H)
A = digital filter zero (R20H)
B = digital filter pole (R21H)