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HCTL-1101 Datasheet, PDF (33/40 Pages) AVAGO TECHNOLOGIES LIMITED – General Purpose Control ICs Position and Velocity Control Low Power CMOS
The actual velocity is computed only in this algorithm and
stored in scratch registers R35H (MSB) and R34H
(LSB). There is no fractional component in the actual ve-
locity registers and they can be read in any order.
The controller tracks the command velocity continuously
until new mode command is given. The system behavior
after a new velocity command is governed only by the
system dynamics until a steady state velocity is reached.
Integral Velocity Mode
Flags: F0 Cleared
F3 Cleared
F5 Set to begin move
Registers Used:
Register
R00H R00D
Function
Flag Register
R26H R38D Acceleration LSB
R27H R39D Acceleration MSB
R3CH R60D Command Velocity
Integral Velocity Control performs continuous veloc-
ity profiling which is specified by command velocity and
command acceleration. Figure 13 shows the capability of
this control algorithm.
The user can change velocity and acceleration any time
to continuously profile velocity in time. Once the speci-
fied velocity is reached, the HCTL-1101 will maintain that
velocity until a new command is specified. Changes be-
tween actual velocities occur at the presently specified
linear acceleration.
The command velocity is an 8-bit two’s-complement
word stored in R3CH. The units of velocity are quadrature
counts/sample time.
The conversion from rpm to quadrature counts/sample
time is shown in equation 9. The Command Velocity regis-
ter (R3CH) contains only integer data and has no fractional
component.
While the overall range of the velocity command is 8 bits,
two’s-complements, the difference between any two se-
quential commands cannot be greater than 7 bits in mag-
nitude (i.e., 127 decimal). For example, when the HCTL-
1101 is executing a command velocity of 40H (+64D),
the next velocity command must fall in the range of 7FH
(+127D), the maximum command range, C1H (-63D), the
largest allowed difference.
The command acceleration is a 16-bit scalar word stored
in R27H and R26H. The upper byte (R27H) is the integer
part and the lower byte (R26H) is the fractional part pro-
vided for resolution. The integer part has a range of 00H to
7FH. The contents of R26H are internally divided by 256 to
produce the fractional resolution.
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