HCTL-1101 Datasheet, PDF (23/40 Pages) AVAGO TECHNOLOGIES LIMITED – General Purpose Control ICs Position and Velocity Control Low Power CMOS

The compensation is a first-order lead filter which in com-
bination with the Sample Timer T (R0FH) affects the dy-
namic step response and stability of the control system.
The Sample Timer, T, determines the rate at which the
control algorithm gets executed. All parameters, A, B, K,
and T, are 8-bit scalars that can be changed by the user
any time.
As shown in equations [2] and [3], the digital filter uses
previously sampled data to calculate D(z). This old inter-
nally sampled data is cleared when the Initialization/Idle
mode is executed.
In Position Control, Integral Velocity Control, and Trapezoi-
dal Profile Control the digital filter is implemented in the
time domain as shown below:
Where:
n
= current sample time
n-1 = previous sample time
MCn = Motor Command Output at n
MCn-1 = Motor Command Output at n-1
Xn = (Command Position –Actual Position) at n
Xn-1 = (Command Position –Actual Position) at n-1
In Proportional Velocity control the digital compensation
filter is implemented in the time domain as:
Where:
Yn = (Command Velocity –Actual Velocity) at n
Sample Timer Register (R0FH)
The contents of this register set the sampling period of
the HCTL- 1101. The sampling period is:
t = 16(T+1) (1/frequency of the external clock) [4]
Where:
T = contents of register R0FH
The Sample Timer has a limit on the minimum allowable
sample time depending on the control mode being ex-
ecuted. The limits are given in Table 4 below.
The minimum value limits are to make sure the internal
programs have enough time to complete proper execu-
tion.
The maximum value of T (R0FH) is FFH (255D). With a 2
MHz clock, the sample time can vary from 64 µsec to 2048
µsec. With a 1 MHz clock, the sample time can vary from
128 µsec to 4096 µsec.
Digital closed-loop systems with slow sampling times will
have lower stability and a lower bandwidth compared
to similar systems with faster sampling times. This rule
of thumb must be balanced by the needs of the veloc-
ity range to be controlled. Velocities are specified to the
HCTL-1101 in terms of quadrature encoder counts per
sample time.
Hardware Description
The Sample Timer consists of a buffer and a decrement
counter. Each time the counter reaches 00H, the Sampler
Timer Value T (value written to R0FH) is loaded from the
buffer into the counter, which immediately begins to dec-
rement from T.
Writing to the Sample Timer Register
Data written to R0FH will be latched into the internal buf-
fer and used by the counter after it completes the pres-
ent sample time cycle by decrementing to 00H. The next
sample time will use the newly written data.
Table 4.
Reading the Sample Timer Register
Reading R0FH gives the values directly from the decre-
menting counter. Therefore, the data read from R0FH will
have a value anywhere between T and 00H, depending
where in the sample time cycle the counter is.
Example :
1. On reset, the value of the timer is preset to 40H.
2. Reading R0FH shows 3EH . . . 2BH . . . 08H . . . 3CH... .
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