HCPL-316J-500E Datasheet, PDF (27/33 Pages) AVAGO TECHNOLOGIES LIMITED – 2.5 Amp Gate Drive Optocoupler with Integrated (VCE) Desaturation Detection and Fault Status Feedback

Auto-Reset
As shown in Figure 72, when the inverting V_IN- input is
connected to ground (non-inverting configuration), the
HCPL-316J can be configured to reset automatically by
connecting RESET to V_IN+. In this case, the gate control
signal is applied to the non-inverting input as well as the
reset input to reset the fault latch every switching cycle.
During normal operation of the IGBT, asserting the reset
input low has no effect. Following a fault condition, the
gate driver remains in the latched fault state until the
gate control signal changes to the ‘gate low’ state and
resets the fault latch. If the gate control signal is a con-
tinuous PWM signal, the fault latch will always be reset
by the next time the input signal goes high. This config-
uration protects the IGBT on a cycle-by-cycle basis and
automatically resets before the next ‘on’ cycle. The fault
outputs can be wire ‘OR’ed together to alert the micro-
controller, but this signal would not be used for control
purposes in this (Auto-Reset) configuration. When the
HCPL- 316J is configured for Auto-Reset, the guaranteed
minimum FAULT signal pulse width is 3 μs.
1 V_IN+
HCPL-316J
2 V_IN-
3 V_CC1
μC
+
–
4 GND1
5 RESET
6 FAULT
CONNECT
TO OTHER
RESETS
7 V_LED1+
8 V_LED1-
CONNECT
TO OTHER
FAULTS
Figure 71. Global-shutdown, global reset configuration.
μC
V_IN+/
RESET
FAULT
1 V_IN+
V_CC
2 V_IN-
3 V_CC1
4 GND1
HCPL-316J
5 RESET
6 FAULT
7 V_LED1+
8 V_LED1-
Resetting Following a Fault Condition
To resume normal switching operation following a fault
condition (FAULT output low), the RESET pin must first
be asserted low in order to release the internal fault
latch and reset the FAULT output (high). Prior to assert-
ing the RESET pin low, the input (V_IN) switching signals
must be configured for an output (V_OL) low state. This
can be handled directly by the microcontroller or by
hardwiring to synchronize the RESET signal with the ap-
propriate input signal. Figure 73a shows how to connect
the RESET to the V_IN+ signal for safe automatic reset in
the noninverting input configuration. Figure 73b shows
how to configure the V_IN+/RESET signals so that a RESET
signal from the microcontroller causes the input to be
in the “output-off” state. Similarly, Figures 73c and 73d
show automatic RESET and microcontroller RESET safe
configurations for the inverting input configuration.
1 V_IN+
HCPL-316J
2 V_IN-
3 V_CC1
μC
+
–
4 GND1
5 RESET
6 FAULT
7 V_LED1+
8 V_LED1-
Figure 72. Auto-reset configuration.
V_IN+
μC
RESET
FAULT
HCPL-316J fig 72
1 V_IN+
V_CC
2 V_IN-
3 V_CC1
4 GND1
HCPL-316J
5 RESET
6 FAULT
7 V_LED1+
8 V_LED1-
Figure 73a. Safe hardware reset for noninverting input
configuration (automatically resets for every V_IN+ input).
27
Figure 73b. Safe hardware reset for noninverting input
configuration.