HCPL-316J-500E Datasheet, PDF (11/33 Pages) AVAGO TECHNOLOGIES LIMITED – 2.5 Amp Gate Drive Optocoupler with Integrated (VCE) Desaturation Detection and Fault Status Feedback

Notes:
1. In accordance with UL1577, each optocoupler is proof tested by applying an insulation test voltage ≥6000 Vrms for 1 second. This test is per-
formed before the 100% production test for partial discharge (method b) shown in IEC/EN/DIN EN 60747-5-2 Insulation Characteristic Table,
if applicable.
2. The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous
voltage rating. For the continuous voltage rating refer to your equipment level safety specification or IEC/EN/DIN EN 60747-5-2 Insulation
Characteristics Table.
3. Device considered a two terminal device: pins 1 - 8 shorted together and pins 9 - 16 shorted together.
4. In order to achieve the absolute maximum power dissipation specified, pins 4, 9, and 10 require ground plane connections and may require
airflow. See the Thermal Model section in the application notes at the end of this data sheet for details on how to estimate junction tem-
perature and power dissipation. In most cases the absolute maximum output IC junction temperature is the limiting factor. The actual power
dissipation achievable will depend on the application environment (PCB Layout, air flow, part placement, etc.). See the Recommended PCB
Layout section in the application notes for layout considerations. Output IC power dissipation is derated linearly at 10 mW/°C above 90°C.
Input IC power dissipation does not require derating.
5. Maximum pulse width = 10 μs, maximum duty cycle = 0.2%. This value is intended to allow for component tolerances for designs with I_O
peak minimum = 2.0 A. See Applications section for additional details on I_OH peak. Derate linearly from 3.0 A at +25°C to 2.5 A at +100°C. This
compensates for increased I_OPEAK due to changes in V_OL over temperature.
6. This supply is optional. Required only when negative gate drive is implemented.
7. Maximum pulse width = 50 μs, maximum duty cycle = 0.5%.
8. See the Slow IGBT Gate Discharge During Fault Condition section in the applications notes at the end of this data sheet for further details.
9. 15 V is the recommended minimum operating positive supply voltage (V_CC2 - V_E) to ensure adequate margin in excess of the maximum V_U-
VLO+ ^{threshold of 13.5 V. For High Level Output Voltage testing, V}OH ^{is measured with a dc load current. When driving capacitive loads, V}OH
will approach V_CC as I_OH approaches zero units.
10. Maximum pulse width = 1.0 ms, maximum duty cycle = 20%.
11. Once V_OUT of the HCPL-316J is allowed to go high (V_CC2 - V_E > V_UVLO), the DESAT detection feature of the HCPL-316J will be the primary
source of IGBT protection. UVLO is needed to ensure DESAT is functional. Once V_UVLO+ > 11.6 V, DESAT will remain functional until V_UVLO- <
12.4 V. Thus, the DESAT detection and UVLO features of the HCPL-316J work in conjunction to ensure constant IGBT protection.
12. See the Blanking Time Control section in the applications notes at the end of this data sheet for further details.
13. This is the “increasing” (i.e. turn-on or “positive going” direction) of V_CC2 - V_E.
14. This is the “decreasing” (i.e. turn-off or “negative going” direction) of V_CC2 - V_E.
15. This load condition approximates the gate load of a 1200 V/75A IGBT.
16. Pulse Width Distortion (PWD) is defined as |t_PHL - t_PLH| for any given unit.
17. As measured from V_IN+, V_IN- to V_OUT.
18. The difference between t_PHL and t_PLH between any two HCPL-316J parts under the same test conditions.
19. Supply Voltage Dependent.
20. This is the amount of time from when the DESAT threshold is exceeded, until the FAULT output goes low.
21. This is the amount of time the DESAT threshold must be exceeded before V_OUT begins to go low, and the FAULT output to go low.
22. This is the amount of time from when RESET is asserted low, until FAULT output goes high. The minimum specification of 3 μs is the guaran-
teed minimum FAULT signal pulse width when the HCPL-316J is configured for Auto-Reset. See the Auto-Reset section in the applications
notes at the end of this data sheet for further details.
23. Common mode transient immunity in the high state is the maximum tolerable
dV_CM/dt of the common mode pulse, V_CM, to assure that the output will remain in the high state (i.e., V_O > 15 V or FAULT > 2 V). A 100 pF and
a 3K Ω pull-up resistor is needed in fault detection mode.
24. Common mode transient immunity in the low state is the maximum tolerable dV_CM/dt of the common mode pulse, V_CM, to assure that the
output will remain in a low state (i.e., V_O < 1.0 V or FAULT < 0.8 V).
25. Does not include LED2 current during fault or blanking capacitor discharge current.
26. To clamp the output voltage at V_CC - 3 V_BE, a pull-down resistor between the output and V_EE is recommended to sink a static current of 650
μA while the output is high. See the Output Pull-Down Resistor section in the application notes at the end of this data sheet if an output pull-
down resistor is not used.
27. The recommended output pull-down resistor between V_OUT and V_EE does not contribute any output current when V_OUT = V_EE.
28. In most applications V_CC1 will be powered up first (before V_CC2) and powered down last (after V_CC2). This is desirable for maintaining control
of the IGBT gate. In applications where V_CC2 is powered up first, it is important to ensure that V_in+ remains low until V_CC1 reaches the proper
operating voltage (minimum 4.5 V) to avoid any momentary instability at the output during V_CC1 ramp-up or ramp-down.
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