HCPL-316J-500E Datasheet, PDF (25/33 Pages) AVAGO TECHNOLOGIES LIMITED – 2.5 Amp Gate Drive Optocoupler with Integrated (VCE) Desaturation Detection and Fault Status Feedback

HCPL-316J
V_E 16
V_LED2+ 15
DESAT 14
V_CC2 13
V_C 12
V_OUT 11
V_EE 10
V_EE 9
R_g
R_PULL-DOWN
Figure 65. Output pull-down resistor.
HCPL-316J
V_E 16
V_LED2+ 15
DESAT 14
V_CC2 13
V_C 12
V_OUT 11
V_EE 10
V_EE 9
100 pF
100 Ω _DDESAT
R_g
μC
3.3
+
–
kΩ
330 pF
1 V_IN+
2 V_IN-
3 V_CC1
4 GND1
HCPL-316J
5 RESET
6 FAULT
7 V_LED1+
8 V_LED1-
Figure 66. DESAT pin protection.
Figure 67. FAULT pin CMR protection.
Other Recommended Components
The application circuit in Figure 62 includes an output
pull-down resistor, a DESAT pin protection resistor, a
FAULT pin capacitor (330 pF), and a FAULT pin pull-up
resistor.
Output Pull-Down Resistor
During the output high transition, the output voltage
rapidly rises to within 3 diode drops of V_CC2. If the output
current then drops to zero due to a capacitive load, the
output voltage will slowly rise from roughly V_CC2-3(V_BE)
to V_CC2 within a period of several microseconds. To limit
the output voltage to V_CC2-3(V_BE), a pull-down resistor
between the output and V_EE is recommended to sink a
static current of several 650 μA while the output is high.
Pull-down resistor values are dependent on the amount
of positive supply and can be adjusted according to the
formula, R_pull-down = [V_CC2-3 * (V_BE)] / 650 μA.
DESAT Pin Protection
The freewheeling of flyback diodes connected across
the IGBTs can have large instantaneous forward voltage
transients which greatly exceed the nominal forward
voltage of the diode. This may result in a large negative
voltage spike on the DESAT pin which will draw substan-
tial current out of the IC if protection is not used. To limit
this current to levels that will not damage the IC, a 100
ohm resistor should be inserted in series with the DE-
SAT diode. The added resistance will not alter the DESAT
threshold or the DESAT blanking time.
Capacitor on FAULT Pin for High CMR
Rapid common mode transients can affect the fault
pin voltage while the fault output is in the high state. A
330 pF capacitor (Fig. 66) should be connected between
the fault pin and ground to achieve adequate CMOS
noise margins at the specified CMR value of 15 kV/μs.
The added capacitance does not increase the fault out-
put delay when a desaturation condition is detected.
Pull-up Resistor on FAULT Pin
The FAULT pin is an open-collector output and therefore
requires a pull-up resistor to provide a high-level signal.
Driving with Standard CMOS/TTL for High CMR
Capacitive coupling from the isolated high voltage
circuitry to the input referred circuitry is the primary
CMR limitation. This coupling must be accounted for to
achieve high CMR performance. The input pins V_IN+ and
V_IN- must have active drive signals to prevent unwanted
switching of the output under extreme common mode
transient conditions. Input drive circuits that use pull-up
or pull-down resistors, such as open collector configu-
rations, should be avoided. Standard CMOS or TTL drive
circuits are recommended.
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