HCPL-2533 Datasheet, PDF (11/11 Pages) AVAGO TECHNOLOGIES LIMITED – LSTTL compatible

Recommended Circuit Design Parameters
Parameter
Symbol LSTTL
LSTTL-to-
LSTTL
TTL-to-
Units
Comments
Fig. Note
Input
Logic Low Output
V_OL (A) 0.5
0.4
Voltage – Input Gate
V
Maximum
Supply Voltage – Input
V_CC1
5.0
5.0
V
± 5%
Input Resistor
R_IN
360
180
Ω
± 5%
8a
430
200
8b
Input Current
I_F
8
16
mA
Nominal
Input Current Range
I_F
6.75–10 14.0–20 mA
8a
14.5–20
8b
Output
Logic Low Output
V_OL (B) 0.5
0.5
Voltage – HCPL-2533
V
Maximum
Supply Voltage – Input
V_CC2
5.0
5.0
V
± 5%
Pull-Up Resistor
R_L
20
8.2
kΩ
± 5%
13
Required Current Sink
I_OL
0.61
1.0
mA
Worst Case V_CC,
14
for Logic Low
(max)
R_L, I_IL (B)
HCPL-2533 Current
Transfer Ratio
CTR
11
9
%
Minimum T_A = 0°C to
+70°C
Logic Low Output
Current – HCPL-2533
I_OL
0.74
1.26
(min)
1.30
mA
Worst Case V_CC, CTR, I_F 8a 15
T_A = 0°C to +70°C
8b
Data Rate
f_D
250
250
Kb/s
NRZ, T_A = 25°C
16
Notes:
12. The inverting circuit has higher power consumption and must use open collector gates on the input.
13. The load resistor R_L must be large enough to guarantee logic LOW and small enough to guarantee logic HIGH under worst case conditions:
V_CC (max) – V_OL
I_OL (2533) – I_IL (B)
≤ R_L ≤
V_CC (min) – V_IH (B)
I_OH (2533) – I_IH (B)
The selection of R_L is the same for both inverting and non-inverting circuits.
14. The maximum current sink required for logic LOW is:
I_OL (max) = I_IL (B) (max) + I_R (max)
where I_R is the current through R_L.
15. The ratio of I_OL (min) to I_OL (max) gives the design margin for CTR degradation. See Application Note 1002.
16. The maximum data rate is defined as:
1
f_{D  = t PH L} + t _{P LH}    bits/second NRZ
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Data subject to change. Copyright © 2007 Avago Technologies Limited. All rights reserved. Obsoletes 5953-0458
AV02-0521EN - June 19, 2007