DS125DF410_13 Datasheet, PDF(28/44 Page) Texas Instruments – DS125DF410 Low Power Multi-Rate Quad Channel Retimer

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DS125DF410_13 Datasheet, PDF (28/44 Pages) Texas Instruments – DS125DF410 Low Power Multi-Rate Quad Channel Retimer

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DS125DF410

SNLS398E â JANUARY 2012 â REVISED MAY 2013

www.ti.com

If the DS125DF410 loses lock because of a change in the CTLE settings, the DS125DF410 will initiate its lock

and adaptation sequence again. Thus, if you write new CTLE boost values to register 0x03 and 0x13 which

cause the DS125DF410 to drop out of lock, the DS125DF410 may, in the process of reacquiring the CDR lock,

reset the CTLE settings to different values than those you set in register 0x03 and 0x13. If this behavior is not

understood, it can appear that the DS125DF410 did not accept the values you wrote to the CTLE boost registers.

What's really happening, however, is that the lock and adaptation sequence is overriding the CTLE values you

wrote to the CTLE boost registers. This will not happen unless the DS125DF410 drops out of lock.

if the adapt mode is set to 0 (bits 6:5 of channel register 0x31), then the CTLE boost values will not be

overridden, but the DS125DF410 may still lose lock. If this happens, the DS125DF410 will attempt to reacquire

lock. if the reference mode is set appropriately, and if the rate/subrate code is set to permit it, the DS125DF410

will begin searching for CDR lock at the highest allowable VCO divider ratio â that is, at the lowest configured bit

rate. At divider values of 4 and 8, the CTLE boost settings used will come not from the values in register 0x03,

and 0x13, but rather from register 0x3a, the fixed CTLE boost setting for lower data rates. This setting will be

written into boost setting register 0x03 during the lock search process. This value may be different from the value

you set in register 0x03, so, again, it may appear that the DS125DF410 has not accepted the CTLE boost

settings you set in registers 0x03 and 0x13. The interactions of the lock and adaptation sequences with the

manually-set CTLE boost settings can be difficult to understand.

To manually override the CTLE boost under all conditions, perform the following steps.

1. Set the DS125DF410 channel adapt mode to 0 by writing 0x0 to bits 6:5 of channel register 0x31.

2. Set the desired CTLE boost setting in register 0x3a. If the DS125DF410 loses lock and attempts to lock to a

lower data rate, it will use this CTLE boost setting.

3. Set the desired CTLE boost setting in register 0x03.

4. Set the desired CTLE boost setting in register 0x40.

5. If desired, set the CTLE stage 3 limiting bit, bit 2 of register 0x13.

If the DS125DF410 loses lock when the CTLE boost settings are set according to the sequence above, the

DS125DF410 will try to reacquire lock, but it will not change the CTLE boost settings in order to do so.

Overriding the VCO Search Values

0x2f, bits 7:6 and 5:4

Registers 0x08 and 0x0b contain CAP DAC override values. Normally, when bits 5:4 of register 0x36 are set to

2'b11, then the DS125DF410 performs an initial search to determine the correct CAP DAC setting (coarse VCO

tuning) for the selected rate and subrate. The rate and subrate settings (bits 7:6 and 5:4 of register 0x2f)

determine the frequency range to be searched, with the 25 MHz reference clock used as the frequency reference

for the frequency search.

The CAP DAC value can be overridden by writing new values to bits 4:0 of register 0x08 (for CAP DAC setting 1)

and bits 4:0 of 0x0b (for CAP DAC setting 2). The override bit, bit 7 of register 0x09 must be set for the override

CAP DAC values to take effect. Since the valid rate and subrate setting for 10 GbE and 1 GbE applies to multiple

data rates, there are two CAP DAC values for this rate. The first is in register 0x08, bits 4:0, and the second is in

(8) associated with the selected rate and subrate to try and acquire lock. If it fails to acquire lock, it will use the

CAP DAC value in register 0x0b with the smaller divide ratio (higher VCO frequency) associated with the

selected rate and subrate (1). It will continue to try to acquire lock in this way until it either succeeds or the

override bit (bit 7 of register 0x09) is cleared.

Overriding the Output Multiplexer

By default, the DS125DF410 output for each channel will be as shown in Table 8.

Input Signal Status

Not Present

Present

Table 8. Default Output Status Description

Channel Status

No Signal Detected

Not Locked

Output Status

Muted

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