DS125DF410_13 Datasheet, PDF (12/44 Pages) Texas Instruments – DS125DF410 Low Power Multi-Rate Quad Channel Retimer

DS125DF410
SNLS398E – JANUARY 2012 – REVISED MAY 2013
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CTLE Boost Setting
The CTLE is a four-stage amplifier with an adjustable, quasi-high-pass transfer function on each stage. The
overall frequency response of the CTLE is set by adjusting the boost of each stage independently. Each stage of
the CTLE can be set to one of four boost settings. The amount of high-frequency boost supplied by each stage
generally increases with increasing boost settings.
The CTLE can also be configured to adapt automatically to provide the optimum boost level for its input signal.
Automatic adaptation of the CTLE only is the default mode of operation for the DS125DF410.
DFE Tap Weight and Polarity Setting
The DS125DF410 includes a five-tap decision-feedback equalizer (DFE) which operates on the signal at the
output of the CTLE.
When the tap weights and polarities are properly set, the DFE approximates a matched filter for the input
transmission channel frequency response as modified by the CTLE frequency response. The CTLE and the DFE
work together to compensate for the input transmission channel response.
The DFE discriminates against input noise and random jitter as well as against crosstalk at the input to the
DS125DF410. When the DFE tap weights and polarities are properly set the DS125DF410 CDR operates at an
acceptable BER with more severe channel impairments than can be compensated with the CTLE alone.
It is possible to automatically or manually set the tap weights and polarities in the DS125DF410. Determining the
correct tap weights manually is difficult and time-consuming, so the DS125DF410 is designed to automatically
adapt the DFE tap weights and polarities in normal operation. This automatic adaptation provides superior BER
performance for noisy channels and channels subject to crosstalk aggressors.
The DFE is powered down by default. In order for the DFE tap weights and polarities to be applied to the input
signal, bit 3 of register 0x1e, the dfe_PD bit, should be set to 0 to power up the DFE. Also the adapt mode
setting in register 0x31, bits[6:5] should be set to 2b'10 or 2b'11 so the device can automatically adapt the CTLE
and DFE.
Rate and Subrate Setting
Register 0x2f, bits 7:4, Registers 0x60, 0x61, 0x62, 0x63, and 0x64
The DS125DF410 is part of a family of retimer devices differentiated by different VCO frequency ranges. Each
device in the retimer family is designed for operation in specific frequency bands and with specific data rate
standards.
The DS125DF410 is designed to lock rapidly to any valid signal present at its inputs. It is also designed to detect
incorrect lock conditions which can arise when the input data signals are strongly periodic. This condition is
referred to as “false lock”. The DS125DF410 discriminates against false lock by using its 25 MHz reference to
ensure that the VCO frequency resulting from its internal phase-locking process is correct.
To determine the correct VCO frequency, the digital circuitry in the DS125DF410 requires some user-supplied
information about the expected data rate or data rates. This information is provided by writing several device
registers using the SMBus.
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