DS125DF410_13 Datasheet, PDF (21/44 Pages) Texas Instruments – DS125DF410 Low Power Multi-Rate Quad Channel Retimer

DS125DF410
www.ti.com
SNLS398E – JANUARY 2012 – REVISED MAY 2013
Table 5. Control/Shared Registers
Address (Hex) Bits
0x00
7:4
0x01
7:5
4:0
0x04
6
5
4
0x05
7
4
3
2
1
0
0x06
3:0
0xff
3
2
1:0
Default Value (Hex)
0x0
0x6
0x11
0x0
0x0
0x0
0x0
(1)
0x0
0x0
0x0
0x0
0X0
0x0
0x0
0x0
Mode
R
R
R
R/W/SC
R/W
R/W
R/W
R
R
R
R
R
R/W
R/W
R/W
R/W
Description
SMBus Address Strap Observation <3:0>
Device Revision
Device ID
Self-Clearing Reset for Control/Shared Registers
Reset for SMBus Master Mode
Force EEPROM Configuration
Disable Master Mode EEPROM Configuration
EEPROM Read Complete
Set on Channel 0 Interrupt
Set on Channel 1 Interrupt
Set on Channel 2 Interrupt
Set on Channel 3 Interrupt
Diagnostic Test Control
Set to 0xa to read SMBus strap values from register 0x00
Selects All Channels for Register Write
See Table 6
Enables Register Write to One or All Channels and Register Read
from One Channel
See Table 6
Selects Target Channel for Register Reads and Writes
See Table 6
(1) There is no default value. This bit always indicates whether the EEPROM read is complete or not.
SMBus Strap Observation
Register 0x00, bits 7:4 and register 0x06, bits 3:0
In order to communicate with the DS125DF410 over the SMBus, it is necessary for the SMBus controller to know
the address of the DS125DF410 . The address strap observation bits in control/shared register 0x00 are primarily
useful as a test of SMBus operation. There is no way to get the DS125DF410 to tell you what its SMBus address
is unless you already know what it is.
In order to use the address strap observation bits of control/shared register 0x00, it is necessary first to set the
diagnostic test control bits of control/shared register 0x06. This four-bit field should be written with a value of 0xa.
When this value is written to bits 3:0 of control/shared register 0x06, then the value of the SMBus address straps
can be read in register 0x00, bits 7:4. The value read will be the same as the value present on the
ADDR3:ADDR0 lines when the DS125DF410 was powered up. For example, if a value of 0x1 is read from
control/shared register 0x00, bits 7:4, then at power-up the ADDR0 line was set to 1 and the other address lines,
ADDR3:ADDR1, were all set to 0. The DS125DF410 is set to an SMBus Write address of 0x32.
Device Revision and Device ID
Register 0x01
Control/shared register 0x01 contains the device revision and device ID. The device revision shown in Table 5 is
the current revision for the DS125DF410. The device ID will be different for the different devices in the retimer
family. This register is useful because it can be interrogated by software to determine the device variant and
revision installed in a particular system. The software might then configure the device with appropriate settings
depending upon the device variant and revision.
Control/Shared Register Reset
Register 0x04, bit 6
Register 0x04, bit 6, clears all the control/shared registers back to their factory defaults. This bit is self-clearing,
so it is cleared after it is written and the control/shared registers are reset to their factory default values.
Interrupt Channel Flag Bits
Register 0x05, bits 3:0
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