DS125DF410_13 Datasheet, PDF (23/44 Pages) Texas Instruments – DS125DF410 Low Power Multi-Rate Quad Channel Retimer

DS125DF410
www.ti.com
SNLS398E – JANUARY 2012 – REVISED MAY 2013
Table 6. Channel Select Register Values Mapped to Register Set Target
Register 0xff Value (hex) Shared/Channel
Register Selection
0x00
Shared
0x04
Channel
0x05
Channel
0x06
Channel
0x07
Channel
0x0c
Channel
Broadcast Channel
Register Selection
N/A
No
No
No
No
Yes
Targeted Channel
Selection
N/A
0
1
2
3
0
0x0d
Channel
Yes
1
0x0e
Channel
Yes
2
0x0f
Channel
Yes
3
Comments
All reads and writes target
shared register set
All reads and writes target
channel 0 register set
All reads and writes target
channel 1 register set
All reads and writes target
channel 2 register set
All reads and writes target
channel 3 register set
All writes target all
channel register sets, all
reads target channel 0
register set
All writes target all
channel register sets, all
reads target channel 1
register set
All writes target all
channel register sets, all
reads target channel 2
register set
All writes target all
channel register sets, all
reads target channel 3
register set
Reading to and Writing from the Channel Registers
Each of the four channels has a complete set of channel registers associated with it. The channel registers or the
control/shared registers are selected by channel select register 0xff. The settings in this register control the target
for subsequent register reads and writes until the contents of register 0xff are explicitly changed by a register
write to register 0xff. As noted, there is only one register with an address of 0xff, the channel select register.
Address (Hex) Bits
0x00
2
0x01
4
0
0x02
7:0
0x03
7:6
5:4
3:2
1:0
0x08
4:0
Table 7. Channel Registers
Default Value (Hex) Mode
0x0
R/W/SC
0x0
R
0x0
R
0x0
R
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x00
R/W
Field Name
rst_regs
cdr_lock_loss_int
signal_detect_loss_int
cdr_status
eq_BST0[1:0]
eq_BST1[1:0]
eq_BST2[1:0]
eq_BST3[1:0]
cdr_cap_dac_start[4:0]
Description
Reset Channel Registers to Defaults (Self-
clearing)
CDR Lock Loss Interrupt
Signal Detect Loss Interrupt
CDR Status [7:0]
Bit[7] = PPM Count met
Bit[6] = Auto Adapt Complete
Bit[5] = Fail Lock Check
Bit[4] = Lock
Bit[3] = CDR Lock
Bit[2] = Single Bit Limit Reached
Bit[1] = Comp LPF High
Bit[0] = Comp LPF Low
CTLE Boost Stage 0 <1:0>
CTLE Boost Stage 1 <1:0>
CTLE Boost Stage 2 <1:0>
CTLE Boost Stage 3 <1:0>
Override Starting VCO Cap DAC Setting 0
<4:0>
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