DS125DF410_13 Datasheet, PDF (19/44 Pages) Texas Instruments – DS125DF410 Low Power Multi-Rate Quad Channel Retimer

DS125DF410
www.ti.com
SNLS398E – JANUARY 2012 – REVISED MAY 2013
The DS125DF410 can be configured with any of 16 SMBus addresses. The SMBus addressing scheme uses the
least-significant bit of the SMBus address as the Read/Write_N address bit. When an SMBus device is
addressed for writing, this bit is set to 0; for reading, to 1. Table 4 below shows the write address setting for the
DS125DF410 versus the values latched in on the address lines at power-up.
The address byte sent by the SMBus master over the SMBus is always 8 bits long. The least-significant bit
indicates whether the address is for a write operation, in which the master will output data to the SMBus to be
read by the slave, or a read operation, in which the slave will output data to the SMBus to be read by the master.
if the least-significant bit is a 0, the address is for a write operation. If it is a 1, the address is for a read
operation. Accordingly, SMBus addresses are sometimes referred to as seven-bit addresses. To produce the
write address for the SMBus, the seven-bit address is left-shifted by one bit. To produce the read address, it is
left shifted by one bit and the least-significant bit is set to 1. Table 4 shows the seven-bit addresses
corresponding to each set of address line values.
When the DS125DF410 is used in SMBus slave mode, the READ_EN pin must be tied low. If it is tied high or
floating, the DS125DF410 will not latch in its address from the address lines on power-up. When the READ_EN
pin is tied high in SMBus slave mode i.e. when the EN_SMB pin (pin 20) is tied high, the DS125DF410 will revert
to an SMBus write address of 0x30. This is a test feature. If there are multiple DS125DF410s on the same
SMBus, they will all revert to an SMBus write address of 0x30, which can cause SMBus collisions and failure to
access the DS125DF410s over the SMBus.
ADDR_3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Table 4. DS125DF410 SMBus Write Address Assignment
ADDR_2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
ADDR_1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
ADDR_0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
SMBus Write
Address
0x30
0x32
0x34
0x36
0x38
0x3a
0x3c
0x3e
0x40
0x42
0x44
0x46
0x48
0x4a
0x4c
0x4e
Seven-bit SMBus
Address
0x18
0x19
0x1a
0x1b
0x1c
0x1d
0x1e
0x1f
0x20
0x21
0x22
0x23
0x24
0x25
0x26
0x27
Once the DS125DF410 has latched in its SMBus address, its registers can be read and written using the two
pins of the SMBus interface, Serial Data (SDA) and Serial Data Clock (SDC).
SDA and SDC
In both SMBus master and SMBus slave mode, the DS125DF410 is configured using the SMBus. The SMBus
consists of two lines, the SDA or serial data line (pin 18) and the SDC or serial clock line (pin 17). In the
DS125DF410 these pins are 3.3V tolerant. The SDA and SDC lines are both open-drain. They require a pull-up
resistor to a supply voltage, which may be either 2.5V or 3.3V. A pull-up resistor in the 2KΩ to 5KΩ range will
provide reliable SMBus operation.
The SMBus is a standard communications bus for configuring simple systems. For a specification of the SMBus
an description of its operation, see smbus.org/specs/.
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