DS125DF410_13 Datasheet, PDF (27/44 Pages) Texas Instruments – DS125DF410 Low Power Multi-Rate Quad Channel Retimer

DS125DF410
www.ti.com
SNLS398E – JANUARY 2012 – REVISED MAY 2013
If the interrupt has occurred because the horizontal or vertical eye opening has dropped below the pre-set
threshold, which is set in channel register 0x32, then bit 4 of register 0x30 will go high. This indicates that the
source of the interrupt was the HEO or VEO.
If the interrupt has occurred because the CDR has fallen out of lock, or because the signal is no longer detected
at the input, then bit 4 and/or bit 0 of register 0x01 will go high, indicating the cause of the interrupt.
In either case, the control/shared register set will indicate which channel caused the interrupt. This is read from
bits 3:0 of control/shared register 0x05.
When an interrupt is detected by the controller on the interrupt input, the controller should take the following
steps to determine the cause of the interrupt and clear it.
1. The controller detects the interrupt by detecting that the INT line has been pulled low by one of the retimers
to which it is connected.
2. The controller reads control/shared register 0x05 from all the DS125DF410s connected to the INT line. For at
least one of these devices, at least one of the bits 3:0 will be set in this register.
3. For each device with a bit set in bits 3:0 of control/shared register 0x05, the controller determines which
channel or channels produced an interrupt. Refer to Table 5 for a mapping of the bits in this bit field to the
channel producing the interrupt.
4. When the controller detects that one of the retimers has a 1 in one of the four LSBs of this register, the
controller selects the channel register set for that channel of that retimer by writing to the channel select
register, 0xff, as previously described.
5. For each channel that generated an interrupt, the controller reads channel register 0x01. If bit 4 of this
register is set, then the interrupt was caused by a loss of CDR lock. If bit 0 is set, then the interrupt was
caused by a loss of signal. it is possible that both bits 0 and 4 could be set. Reading this register will clear
these bits.
6. Optionally, for each channel that generated an interrupt, the controller reads channel register 0x30. If bit 4 of
this register is set, then the interrupt was caused by HEO and/or VEO falling out of the configured range.
This interrupt will only occur if bit 6 of channel register 0x36 is set, enabling the HEO/VEO interrupt. Reading
register 0x30 will clear this interrupt bit.
7. Once the controller has determined what condition caused the interrupt, the controller can then take the
appropriate action. For example, the controller might reset the CDR to cause the retimer to re-adapt to the
incoming signal. If there is no longer an incoming signal (indicated by a loss of signal interrupt, bit 0 of
channel register 0x01), then the controller might alert an operator or change the channel configuration. This
is system dependent.
8. Reading the interrupt status registers will clear the interrupt. If this does not cause the interrupt input to go
high, then another device on the same input has generated an interrupt. The controller can address the next
device using the procedure above.
9. Once all the interrupt registers for all channels for all DS125DF410s that generated interrupts have been
read, clearing all the interrupt indications, the INT line should go high again. This indicates that all the
existing interrupt conditions have been serviced.
The channel registers referred to above, registers 0x01, 0x30, 0x32, and 0x36, are described in the channel
registers table, Table 7.
Overriding the CTLE Boost Setting
Register 0x03, Register 0x13, bit 2, and Register 0x3a
To override the CTLE boost settings, register 0x03 is used. This register contains the currently-applied CTLE
boost settings. The boost values can be overridden by using the two-bit fields in this register as shown in the
table.
The final stage of the CTLE has an additional control bit which sets it to a limiting mode. For some channels, this
additional setting improves the bit error rate performance. This bit is bit 2 of register 0x13.
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