DS125DF410_13 Datasheet, PDF (1/44 Pages) Texas Instruments – DS125DF410 Low Power Multi-Rate Quad Channel Retimer

DS125DF410
www.ti.com
SNLS398E – JANUARY 2012 – REVISED MAY 2013
DS125DF410 Low Power Multi-Rate Quad Channel Retimer
Check for Samples: DS125DF410
FEATURES
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•2 Each Channel Independently Locks to Data
Rates from 9.8 to 12.5 Gbps and Submultiples
• Fast Lock Operation Based on Protocol-Select
Mode
• Low Latency (~300ps)
• Adaptive Equalization up to 34 dB Boost at 5
GHz
• Adjustable Transmit V_OD : 600 to 1300 mVp-p
• Adjustable Transmit De-emphasis to -15 dB
• Typical Power Dissipation (EQ+DFE+CDR+DE):
180 mW /Channel
• Programmable Output Polarity Inversion
• Input Signal Detection, CDR Lock
Detection/Indicator
• On-Chip Eye Monitor (EOM), PRBS Generator
• Single 2.5 V ±5% Power Supply
• SMBus/EEPROM Configuration Modes
• Operating Temperature Range of -40 to 85°C
• RHS (QFN) 48-Pin 7 mm x 7 mm Package
• Easy Pin Compatible Upgrade Between
Repeater and Retimers
– DS100RT410 (EQ+CDR+DE): 10.3125 Gbps
– DS100DF410 (EQ+DFE+CDR+DE): 10.3125
Gbps
– DS110RT410 (EQ+CDR+DE): 8.5 - 11.3 Gbps
– DS110DF410 (EQ+DFE+CDR+DE): 8.5 - 11.3
Gbps
– DS125RT410 (EQ+CDR+DE): 9.8 - 12.5 Gbps
– DS125DF410 (EQ+DFE+CDR+DE): 9.8 - 12.5
Gbps
– DS100BR410 (EQ+DE): Up to 10.3125 Gbps
APPLICATIONS
• Front Port SFF 8431 (SFP+) Optical and Direct
Attach Copper
• Backplane Reach Extension, Data Retimer
• Ethernet: 10GbE, 1GbE
• CPRI: Line Bit Rate Options 3–7
• Interlaken: All Lane Bit Rates
• InfiniBand
• Other Propriety Data Rates up to 12.5 Gbps
DESCRIPTION
The DS125DF410 is four channel retimer with
integrated signal conditioning. The device includes a
fully adaptive Continuous-Time Linear Equalizer
(CTLE), self calibrating 5-tap Decision Feedback
Equalizer (DFE), Clock and Data Recovery (CDR),
and transmit De-Emphasis (DE) driver to enable data
transmission over long, lossy and crosstalk-impaired
highspeed serial links to achieve BER < 1×10^-15.
Each channel can independently lock to data rate
from 9.8 to 12.5 Gbps, and associated sub rates (div
by 2, 4 and 8) to support a variety of communication
protocols. A 25 MHz crystal oscillator clock is used to
speed up the CDR lock process. This clock is not
used for training the PLL and does not need to be
synchronous with the serial data.
The programmable settings can be applied using the
SMBus (I2C) interface, or they can be loaded via an
external EEPROM. An on-chip eye monitor and a
PRBS generator allow real-time measurement of
high-speed serial data for system bring-up or field
tuning.
The device is offered in a RHS (QFN) 48-pin, 7 mm x
7 mm package. A flow-through pinout for the high
speed signals and a single power supply makes the
DS125DF410 easy to use.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
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2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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