AT91CAP9S500A_1 Datasheet, PDF (999/1137 Pages) ATMEL Corporation – Customizable Microcontroller Processor

AT91CAP9S500A/AT91CAP9S250A
The host updates the backbuffer while the LCD Controller is displaying the primary buffer. When
the backbuffer has been updated the host updates the DMA Base Address registers.
When using a Dual Panel LCD Module, both base address pointers should be updated in the
same frame. There are two possibilities:
• Check the DMAFRMPTx register to ensure that there is enough time to update the DMA
Base Address registers before the end of frame.
• Update the Frame Base Address Registers when the End Of Frame IRQ is generated.
Once the host has updated the Frame Base Address Registers and the next DMA end of frame
IRQ arrives, the backbuffer and the primary buffer are swapped and the host can work with the
new backbuffer.
When using a dual-panel LCD module, both base address pointers should be updated in the
same frame. In order to achieve this, the DMAUPDT bit in DMACON register must be used to
validate the new base address.
46.9
2D Memory Addressing
The LCDC can be configured to work on a frame buffer larger than the actual screen size. By
changing the values in a few registers, it is easy to move the displayed area along the frame buf-
fer width and height.
Figure 46-11. Frame Buffer Addressing
Frame Buffer
Base word address &
pixel offset
Displayed Image
Line-to-line
address increment
6264C–CAP–24-Mar-09
999