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AT91CAP9S500A_1 Datasheet, PDF (623/1137 Pages) ATMEL Corporation – Customizable Microcontroller Processor | |||
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AT91CAP9S500A/AT91CAP9S250A
36.7.15 USART Manchester Configuration Register
Name:
US_MAN
Addresses:
0xFFF8C050 (0), 0xFFF90050 (1), 0xFFF94050 (2)
Access:
Read-write
31
30
29
28
27
26
â
DRIFT
1
RX_MPOL
â
â
25
24
RX_PP
23
22
21
20
19
18
17
16
â
â
â
â
RX_PL
15
14
13
12
11
10
â
â
â
TX_MPOL
â
â
9
8
TX_PP
7
6
5
4
3
2
1
0
â
â
â
â
TX_PL
This register can only be written if the WPEN bit is cleared in âUSART Write Protect Mode Registerâ on page 103.
⢠TX_PL: Transmitter Preamble Length
0: The Transmitter Preamble pattern generation is disabled
1 - 15: The Preamble Length is TX_PL x Bit Period
⢠TX_PP: Transmitter Preamble Pattern
TX_PP
0
0
0
1
1
0
1
1
Preamble Pattern default polarity assumed (TX_MPOL field not set)
ALL_ONE
ALL_ZERO
ZERO_ONE
ONE_ZERO
⢠TX_MPOL: Transmitter Manchester Polarity
0: Logic Zero is coded as a zero-to-one transition, Logic One is coded as a one-to-zero transition.
1: Logic Zero is coded as a one-to-zero transition, Logic One is coded as a zero-to-one transition.
⢠RX_PL: Receiver Preamble Length
0: The receiver preamble pattern detection is disabled
1 - 15: The detected preamble length is RX_PL x Bit Period
⢠RX_PP: Receiver Preamble Pattern detected
RX_PP
0
0
Preamble Pattern default polarity assumed (RX_MPOL field not set)
ALL_ONE
6264CâCAPâ24-Mar-09
623
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