AT91CAP9S500A_1 Datasheet, PDF (601/1137 Pages) ATMEL Corporation – Customizable Microcontroller Processor

AT91CAP9S500A/AT91CAP9S250A
Table 36-11. IrDA Baud Rate Error (Continued)
Peripheral Clock
Baud Rate
CD
40 000 000
57 600
43
3 686 400
38 400
6
20 000 000
38 400
33
32 768 000
38 400
53
40 000 000
38 400
65
3 686 400
19 200
12
20 000 000
19 200
65
32 768 000
19 200
107
40 000 000
19 200
130
3 686 400
9 600
24
20 000 000
9 600
130
32 768 000
9 600
213
40 000 000
9 600
260
3 686 400
2 400
96
20 000 000
2 400
521
32 768 000
2 400
853
Baud Rate Error
0.93%
0.00%
1.38%
0.63%
0.16%
0.00%
0.16%
0.31%
0.16%
0.00%
0.16%
0.16%
0.16%
0.00%
0.03%
0.04%
Pulse Time
3.26
4.88
4.88
4.88
4.88
9.77
9.77
9.77
9.77
19.53
19.53
19.53
19.53
78.13
78.13
78.13
36.6.5.3
IrDA Demodulator
The demodulator is based on the IrDA Receive filter comprised of an 8-bit down counter which is
loaded with the value programmed in US_IF. When a falling edge is detected on the RXD pin,
the Filter Counter starts counting down at the Master Clock (MCK) speed. If a rising edge is
detected on the RXD pin, the counter stops and is reloaded with US_IF. If no rising edge is
detected when the counter reaches 0, the input of the receiver is driven low during one bit time.
Figure 36-35 illustrates the operations of the IrDA demodulator.
Figure 36-35. IrDA Demodulator Operations
MCK
RXD
Counter
Value
Receiver
Input
65432 6
Pulse
Rejected
6543210
Pulse
Accepted
As the IrDA mode uses the same logic as the ISO7816, note that the FI_DI_RATIO field in
US_FIDI must be set to a value higher than 0 in order to assure IrDA communications operate
correctly.
6264C–CAP–24-Mar-09
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