AT91CAP9S500A_1 Datasheet, PDF (63/1137 Pages) ATMEL Corporation – Customizable Microcontroller Processor

AT91CAP9S500A/AT91CAP9S250A
Table 12-2.
Mnemonic
LDRH
LDRB
LDRBT
LDRT
LDM
SWP
MCR
LDC
CDP
ARM Instruction Mnemonic List (Continued)
Operation
Mnemonic
Load Half Word
STRH
Load Byte
STRB
Load Register Byte with
Translation
STRBT
Load Register with Translation
STRT
Load Multiple
STM
Swap Word
SWPB
Move To Coprocessor
MRC
Load To Coprocessor
STC
Coprocessor Data Processing
Operation
Store Half Word
Store Byte
Store Register Byte with
Translation
Store Register with Translation
Store Multiple
Swap Byte
Move From Coprocessor
Store From Coprocessor
12.3.9
New ARM Instruction Set
.
Table 12-3.
Mnemonic
BXJ
New ARM Instruction Mnemonic List
Operation
Mnemonic
Branch and exchange to Java
MRRC
BLX ⁽¹⁾
Branch, Link and exchange
MCR2
SMLAxy
SMLAL
SMLAWy
Signed Multiply Accumulate 16
* 16 bit
Signed Multiply Accumulate
Long
Signed Multiply Accumulate 32
* 16 bit
MCRR
CDP2
BKPT
SMULxy
Signed Multiply 16 * 16 bit
PLD
SMULWy
Signed Multiply 32 * 16 bit
STRD
QADD
Saturated Add
STC2
QDADD
Saturated Add with Double
LDRD
QSUB
Saturated subtract
LDC2
QDSUB
Saturated Subtract with double
CLZ
Operation
Move double from coprocessor
Alternative move of ARM reg to
coprocessor
Move double to coprocessor
Alternative Coprocessor Data
Processing
Breakpoint
Soft Preload, Memory prepare
to load from address
Store Double
Alternative Store from
Coprocessor
Load Double
Alternative Load to
Coprocessor
Count Leading Zeroes
Notes: 1. A Thumb BLX contains two consecutive Thumb instructions, and takes four cycles.
12.3.10
Thumb Instruction Set Overview
The Thumb instruction set is a re-encoded subset of the ARM instruction set.
The Thumb instruction set is divided into:
• Branch instructions
• Data processing instructions
• Load and Store instructions
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