AT91CAP9S500A_1 Datasheet, PDF (690/1137 Pages) ATMEL Corporation – Customizable Microcontroller Processor

38.7.10 AC97 Controller Channel A Mode Register
Name:
AC97C_CAMR
Address: 0xFFFA002C
Access:
Read-write
31
–
23
–
15
RXBUFF
7
–
30
–
22
PDCEN
14
ENDRX
6
–
29
–
21
CEN
13
–
5
OVRUN
28
–
20
–
12
–
4
RXRDY
27
–
19
–
11
TXBUFE
3
–
26
–
18
CEM
10
ENDTX
2
UNRUN
25
–
17
SIZE
9
–
1
TXEMPTY
24
–
16
8
–
0
TXRDY
• TXRDY: Channel Transmit Ready Interrupt Enable
• TXEMPTY: Channel Transmit Empty Interrupt Enable
• UNRUN: Transmit Underrun Interrupt Enable
• RXRDY: Channel Receive Ready Interrupt Enable
• OVRUN: Receive Overrun Interrupt Enable
• ENDTX: End of Transmission for Channel A Interrupt Enable
• TXBUFE: Transmit Buffer Empty for Channel A Interrupt Enable
0: Read: the corresponding interrupt is disabled. Write: disables the corresponding interrupt.
1: Read: the corresponding interrupt is enabled. Write: enables the corresponding interrupt.
• ENDRX: End of Reception for Channel A Interrupt Enable
0: Read: the corresponding interrupt is disabled. Write: disables the corresponding interrupt.
1: Read: the corresponding interrupt is enabled. Write: enables the corresponding interrupt.
• RXBUFF: Receive Buffer Full for Channel A Interrupt Enable
0: Read: the corresponding interrupt is disabled. Write: disables the corresponding interrupt.
1: Read: the corresponding interrupt is enabled. Write: enables the corresponding interrupt.
• SIZE: Channel A Data Size
SIZE Encoding
SIZE
0x0
0x1
0x2
0x3
Selected Data Size
20 bits
18 bits
16 bits
10 bits
Note: Each time slot in the data phase is 20 bit long. For example, if a 16-bit sample stream is being played to an AC 97 DAC, the first
16 bit positions are presented to the DAC MSB-justified. They are followed by the next four bit positions that the AC97 Controller
690 AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09