AT91CAP9S500A_1 Datasheet, PDF (251/1137 Pages) ATMEL Corporation – Customizable Microcontroller Processor

AT91CAP9S500A/AT91CAP9S250A
24.6.5 DDRSDRC Timing 1 Parameter Register
Name:
DDRSDRC_T1PR
Address: 0xFFFFE610
Access: Read-write
Reset:
See Table 24-8
31
30
29
28
27
26
25
24
–
–
–
–
TXP
23
22
21
20
19
18
17
16
TXSRD
15
14
13
12
11
10
9
8
TXSNR
7
6
5
4
3
2
1
0
–
–
–
TRFC
• TRFC: Row Cycle Delay
Reset Value is 8 cycles.
This field defines the delay between a Refresh and an Activate command or Refresh command in number of cycles. Num-
ber of cycles is between 0 and 31
• TXSNR: Exit Self Refresh Delay to Non Read Command
Reset Value is 8 cycles.
This field defines the delay between cke set high and a non Read Command in number of cycles. Number of cycles is
between 0 and 15. This field is used for SDR-SDRAM and DDR-SDRAM devices. In the case of SDR-SDRAM devices and
low-power DDR-SDRAM, this field is equivalent to TXSR timing.
• TXSRD: Exit Self Refresh Delay to Read Command
Reset Value is C8.
This field defines the delay between cke set high and a Read Command in number of cycles. Number of cycles is between
0 and 255 cycles.This field is unique to DDR-SDRAM devices.
• TXP: Exit Power-down Delay to First Command
Reset Value is 3.
This field defines the delay between cke set high and a Valid Command in number of cycles. Number of cycles is between
0 and 15 cycles. This field is unique to low-power DDR-SDRAM devices.
6264C–CAP–24-Mar-09
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