AT91CAP9S500A_1 Datasheet, PDF (1021/1137 Pages) ATMEL Corporation – Customizable Microcontroller Processor

AT91CAP9S500A/AT91CAP9S250A
46.11.24 Power Control Register
Name:
PWRCON
Address:
0x0050083C
Access:
Read-write
Reset:
0x0000000e
31
30
29
28
27
26
25
24
LCD_BUSY
–
–
–
–
–
–
–
23
22
21
20
19
18
17
16
–
–
–
–
–
–
–
–
15
14
13
12
11
10
9
8
–
–
–
–
–
–
–
–
7
6
5
4
3
2
1
0
GUARD_TIME
LCD_PWR
• LCD_PWR: LCD module power control
0 = lcd_pwr signal is low, other lcd_* signals are low.
0->1 = lcd_* signals activated, lcd_pwr is set high with the delay of GUARD_TIME frame periods.
1 = lcd_pwr signal is high, other lcd_* signals are active.
1->0 = lcd_pwr signal is low, other lcd_* signals are active, but are set low after GUARD_TIME frame periods.
• GUARD_TIME
Delay in frame periods between applying control signals to the LCD module and setting LCD_PWR high, and between set-
ting LCD_PWR low and removing control signals from LCD module
• LCD_BUSY
Read-only field. If 1, it indicates that the LCD is busy (active and displaying data, in power on sequence or in power off
sequence).
6264C–CAP–24-Mar-09
1021