AT32AP7000_1 Datasheet, PDF (919/973 Pages) ATMEL Corporation – AVR32 32-bit Microcontroller

AT32AP7000
38.7.2
In many cases, it is not required to shift all bits through the data register. Bit patterns are shown
using the full width of the shift register, but the suggested or required bits are emphasized using
bold text. I.e. given the pattern "aaaaaaar xxxxxxxx xxxxxxxx xxxxxxxx xx", the shift register is
34 bits, but the test or debug unit may choose to shift only 8 bits "aaaaaaar".
The following describes how to interpret the fields in the instruction description tables:
Table 38-4. Instruction description
Instruction
Description
IR input value
Shows the bit pattern to shift into IR in the Shift-IR state in order to select this
instruction. The pattern is show both in binary and in hexadecimal form for
convenience.
Example: 10000 (0x10)
IR output value
Shows the bit pattern shifted out of IR in the Shift-IR state when this instruction is
active.
Example: peb01
DR Size
Shows the number of bits in the data register chain when this instruction is active.
Example: 34 bits
DR input value
Shows which bit pattern to shift into the data register in the Shift-DR state when this
instruction is active. Multiple such lines may exist, e.g. to distinguish between reads
and writes.
Example: aaaaaaar xxxxxxxx xxxxxxxx xxxxxxxx xx
DR output value
Shows the bit pattern shifted out of the data register in the Shift-DR state when this
instruction is active. Multiple such lines may exist, e.g. to distinguish between reads
and writes.
Example: xx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxeb
NEXUS_ACCESS
This instruction allows Nexus-compliant access to on-chip debug registers through the SAB.
OCD registers are addressed by their register index, as listed in the AVR32 Technical Reference
Manual. The 7-bit register index and a read/write control bit, and the 32-bit data is accessed
through the JTAG port.
The data register is alternately interpreted by the SAB as an address register and a data regis-
ter. The SAB starts in address mode after the NEXUS_ACCESS instruction is selected, and
toggles between address and data mode each time a data scan completes with the busy bit
cleared.
NOTE: The polarity of the direction bit is inverse of the Nexus standard.
Starting in Run-Test/Idle, OCD registers are accessed in the following way:
1. Select the DR Scan path
2. Scan in the 7-bit address for the OCD register and a direction bit (1=read, 0=write).
3. Go to Update-DR and re-enter Select-DR Scan
4. For a read operation, scan out the contents of the addressed register. For a write opera-
tion, scan in the new contents of the register.
5. Return to Run-Test/Idle
32003M–AVR32–09/09
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