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AT32AP7000_1 Datasheet, PDF (634/973 Pages) ATMEL Corporation – AVR32 32-bit Microcontroller | |||
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AT32AP7000
31.7.8 Interrupt Status Register
Register Name:
ISR
Access Type:
Read/Write
31
30
29
28
27
26
25
24
â
â
â
â
â
â
â
â
23
22
21
20
19
18
17
16
â
â
â
â
â
â
â
â
15
14
13
12
11
10
9
8
â
â
PTZ
PFR
HRESP
ROVR
-
â
7
6
5
TCOMP
TXERR
RLE
4
TUND
3
TXUBR
2
RXUBR
1
RCOMP
0
MFD
⢠MFD: Management Frame Done
The PHY maintenance register has completed its operation. Cleared on read.
⢠RCOMP: Receive Complete
A frame has been stored in memory. Cleared on read.
⢠RXUBR: Receive Used Bit Read
Set when a receive buffer descriptor is read with its used bit set. Cleared on read.
⢠TXUBR: Transmit Used Bit Read
Set when a transmit buffer descriptor is read with its used bit set. Cleared on read.
⢠TUND: Ethernet Transmit Buffer Underrun
The transmit DMA did not fetch frame data in time for it to be transmitted or hresp returned not OK. Also set if a used bit
is read mid-frame or when a new transmit queue pointer is written. Cleared on read.
⢠RLE: Retry Limit Exceeded
Cleared on read.
⢠TXERR: Transmit Error
Transmit buffers exhausted in mid-frame - transmit error. Cleared on read.
⢠TCOMP: Transmit Complete
Set when a frame has been transmitted. Cleared on read.
⢠ROVR: Receive Overrun
Set when the receive overrun status bit gets set. Cleared on read.
⢠HRESP: Hresp not OK
Set when the DMA block sees a bus error. Cleared on read.
⢠PFR: Pause Frame Received
Indicates a valid pause has been received. Cleared on a read.
⢠PTZ: Pause Time Zero
Set when the pause time register, 0x38 decrements to zero. Cleared on a read.
32003MâAVR32â09/09
634
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