AT32AP7000_1 Datasheet, PDF (610/973 Pages) ATMEL Corporation – AVR32 32-bit Microcontroller

AT32AP7000
Table 31-1. Receive Buffer Descriptor Entry (Continued)
Bit
Function
20
Priority tag detected (i.e., type id of 0x8100 and null VLAN identifier)
19:17 VLAN priority (only valid if bit 21 is set)
16
Concatenation format indicator (CFI) bit (only valid if bit 21 is set)
15
End of frame - when set the buffer contains the end of a frame. If end of frame is not set, then the only other valid status
are bits 12, 13 and 14.
14
Start of frame - when set the buffer contains the start of a frame. If both bits 15 and 14 are set, then the buffer contains a
whole frame.
13:12
Receive buffer offset - indicates the number of bytes by which the data in the first buffer is offset from the word address.
Updated with the current values of the network configuration register. If jumbo frame mode is enabled through bit 3 of the
network configuration register, then bits 13:12 of the receive buffer descriptor entry are used to indicate bits 13:12 of the
frame length.
11:0 Length of frame including FCS (if selected). Bits 13:12 are also used if jumbo frame mode is selected.
To receive frames, the buffer descriptors must be initialized by writing an appropriate address to
bits 31 to 2 in the first word of each list entry. Bit zero must be written with zero. Bit one is the
wrap bit and indicates the last entry in the list.
The start location of the receive buffer descriptor list must be written to the receive buffer queue
pointer register before setting the receive enable bit in the network control register to enable
receive. As soon as the receive block starts writing received frame data to the receive FIFO, the
receive buffer manager reads the first receive buffer location pointed to by the receive buffer
queue pointer register.
If the filter block then indicates that the frame should be copied to memory, the receive data
DMA operation starts writing data into the receive buffer. If an error occurs, the buffer is recov-
ered. If the current buffer pointer has its wrap bit set or is the 1024^th descriptor, the next receive
buffer location is read from the beginning of the receive descriptor list. Otherwise, the next
receive buffer location is read from the next word in memory.
There is an 11-bit counter to count out the 2048 word locations of a maximum length, receive
buffer descriptor list. This is added with the value originally written to the receive buffer queue
pointer register to produce a pointer into the list. A read of the receive buffer queue pointer reg-
ister returns the pointer value, which is the queue entry currently being accessed. The counter is
reset after receive status is written to a descriptor that has its wrap bit set or rolls over to zero
after 1024 descriptors have been accessed. The value written to the receive buffer pointer regis-
ter may be any word-aligned address, provided that there are at least 2048 word locations
available between the pointer and the top of the memory.
The System Bus specification states that bursts should not cross 1K boundaries. As receive buf-
fer manager writes are bursts of two words, to ensure that this does not occur, it is best to write
the pointer register with the least three significant bits set to zero. As receive buffers are used,
the receive buffer manager sets bit zero of the first word of the descriptor to indicate used. If a
receive error is detected the receive buffer currently being written is recovered. Previous buffers
are not recovered. Software should search through the used bits in the buffer descriptors to find
out how many frames have been received. It should be checking the start-of-frame and end-of-
frame bits, and not rely on the value returned by the receive buffer queue pointer register which
changes continuously as more buffers are used.
32003M–AVR32–09/09
610