AT32AP7000_1 Datasheet, PDF (373/973 Pages) ATMEL Corporation – AVR32 32-bit Microcontroller

AT32AP7000
23.9.4 Receive Frame Mode Register
Name:
RFMR
Access Type:
Read/Write
Offset:
0x14
Reset value:
0x00000000
31
30
29
28
27
26
25
24
FSLENHI
–
–
–
FSEDGE
23
22
21
20
19
18
17
16
–
FSOS
FSLEN
15
14
13
12
11
10
9
8
–
–
–
–
DATNB
7
6
5
4
3
2
1
0
MSBF
–
LOOP
DATLEN
• FSLENHI: Receive Frame Sync Length High part
The four MSB of the FSLEN bitfield.
• FSEDGE: Frame Sync Edge Detection
Determines which edge on Frame Sync will generate the interrupt RXSYN in the SSC Status Register.
FSEDGE
0x0
0x1
Frame Sync Edge Detection
Positive Edge Detection
Negative Edge Detection
• FSOS: Receive Frame Sync Output Selection
FSOS
Selected Receive Frame Sync Signal
RX_FRAME_SYNC Pin
0x0
None
Input-only
0x1
Negative Pulse
Output
0x2
Positive Pulse
Output
0x3
Driven Low during data transfer
Output
0x4
Driven High during data transfer
Output
0x5
Toggling at each start of data transfer
Output
0x6-0x7
Reserved
Undefined
• FSLEN: Receive Frame Sync Length
This field defines the length of the Receive Frame Sync Signal and the number of bits sampled and stored in the Receive
Sync Data Register. When this mode is selected by the START field in the Receive Clock Mode Register, it also deter-
mines the length of the sampled data to be compared to the Compare 0 or Compare 1 register. Note: The four most
significant bits fo this bitfield are in the FSLENHI bitfield.
Pulse length is equal to ({FSLENHI,FSLEN} + 1) Receive Clock periods. Thus, if {FSLENHI,FSLEN} is 0, the Receive
Frame Sync signal is generated during one Receive Clock period.
• DATNB: Data Number per Frame
32003M–AVR32–09/09
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