AT32AP7000_1 Datasheet, PDF (15/973 Pages) ATMEL Corporation – AVR32 32-bit Microcontroller

AT32AP7000
• Configurable coefficients with flexible fixed-point representation.
4.0.3
Debug and Test system
• IEEE1149.1 compliant JTAG and boundary scan
• Direct memory access and programming capabilities through JTAG interface
• Extensive On-Chip Debug features in compliance with IEEE-ISTO 5001-2003 (Nexus 2.0) Class 3
• Auxiliary port for high-speed trace information
• Hardware support for 6 Program and 2 data breakpoints
• Unlimited number of software breakpoints supported
• Advanced Program, Data, Ownership, and Watchpoint trace supported
4.0.4
DMA Controller
• 2 HSB Master Interfaces
• 3 Channels
• Software and Hardware Handshaking Interfaces
– 11 Hardware Handshaking Interfaces
• Memory/Non-Memory Peripherals to Memory/Non-Memory Peripherals Transfer
• Single-block DMA Transfer
• Multi-block DMA Transfer
– Linked Lists
– Auto-Reloading
– Contiguous Blocks
• DMA Controller is Always the Flow Controller
• Additional Features
– Scatter and Gather Operations
– Channel Locking
– Bus Locking
– FIFO Mode
– Pseudo Fly-by Operation
4.0.5
Peripheral DMA Controller
• Transfers from/to peripheral to/from any memory space without intervention of the processor.
• Next Pointer Support, forbids strong real-time constraints on buffer management.
• Eighteen channels
– Two for each USART
– Two for each Serial Synchronous Controller
– Two for each Serial Peripheral Interface
4.0.6
Bus system
• HSB bus matrix with 10 Masters and 8 Slaves handled
– Handles Requests from the CPU Icache, CPU Dcache, HSB bridge, HISI, USB 2.0 Controller,
LCD Controller, Ethernet Controller 0, Ethernet Controller 1, DMA Controller 0, DMA
Controller 1, and to internal SRAM 0, internal SRAM 1, PB A, PB B, EBI and, USB.
15
32003M–AVR32–09/09