AT32AP7000_1 Datasheet, PDF (68/973 Pages) ATMEL Corporation – AVR32 32-bit Microcontroller

AT32AP7000
PICOST.{D,W} – Store PICO Register(s)
Description
Stores the PICO register value(s) to the memory location specified by the addressing mode.
Operation:
I.
*(Rp + (ZE(disp8) << 2)) ← PrHi:PrLo;
II.
*(Rp) ← PrHi:PrLo;
Rp ← Rp+8;
III. *(Rb + (Ri << sa2)) ← PrHi:PrLo;
IV. *(Rp + (ZE(disp8) << 2)) ← Pr;
V.
*(Rp) ← Pr;
Rp ← Rp-4;
VI. *(Rb + (Ri << sa2)) ← Pr;
Syntax:
I.
picost.d
II.
picost.d
III. picost.d
IV. picost.w
V.
picost.w
VI. picost.w
Rp[disp], PrHi:PrLo
Rp++, PrHi:PrLo
Rb[Ri<<sa], PrHi:PrLo
Rp[disp], Pr
Rp++, Pr
Rb[Ri<<sa], Pr
Operands:
I-III. PrHi:PrLo ∈ { INPIX1:INPIX2, OUTPIX2:INPIX0, OUTPIX0:OUTPIX1, COEFF0_B:COEFF0_A,
COEFF1_B:COEFF1_A, COEFF2_B:COEFF2_A, VMU1_OUT:VMU0_OUT,
CONFIG:VMU2_OUT }
IV-VI. Pr ∈ { INPIX0, INPIX1, INPIX2, OUTPIX0, OUTPIX1, OUTPIX2, COEFF0_A, COEFF0_B, COEFF1_A,
COEFF1_B, COEFF2_A, COEFF2_B, VMU0_OUT, VMU1_OUT, VMU2_OUT, CONFIG}
I-II, IV-V.p ∈ {0, 1, …, 15}
I, IV. disp ∈ {0, 4, …, 1020}
III, VI. {b, i} ∈ {0, 1, …, 15}
III, VI. sa ∈ {0, 1, 2, 3}
Opcode
I.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
1
1
1
0
1
0
1
1
1
0
1
0
Rp
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PICO CP#
1
PrLo[3:1]
0
disp8
II.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
1
1
1
0
1
1
1
1
1
0
1
0
Rp
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PICO CP#
0
PrLo[3:1]
0
01
1
1
00
0
0
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32003M–AVR32–09/09