AT32UC3A3256S_1 Datasheet, PDF (912/961 Pages) ATMEL Corporation – AVR32 32-Bit Microcontroller

AT32UC3A3
Table 34-9. Symbol Description
The chip protected bit. Some devices may be set in a protected state where access to chip
p
internals are severely restricted. See the documentation for the specific device for details.
On devices without this possibility, this bit always reads as zero.
r
A direction bit. Set to one to request a read, set to zero to request a write.
s
A size bit. The size encoding is described where used.
x
A don’t care bit. Any value can be shifted in, and output data should be ignored.
In many cases, it is not required to shift all bits through the data register. Bit patterns are shown
using the full width of the shift register, but the suggested or required bits are emphasized using
bold text. I.e. given the pattern "aaaaaaar xxxxxxxx xxxxxxxx xxxxxxxx xx", the shift register is
34 bits, but the test or debug unit may choose to shift only 8 bits "aaaaaaar".
The following describes how to interpret the fields in the instruction description tables:
Table 34-10. Instruction Description
Instruction
Description
IR input value
Shows the bit pattern to shift into IR in the Shift-IR state in order to select this
instruction. The pattern is show both in binary and in hexadecimal form for
convenience.
Example: 10000 (0x10)
IR output value
Shows the bit pattern shifted out of IR in the Shift-IR state when this instruction is
active.
Example: peb01
DR Size
Shows the number of bits in the data register chain when this instruction is active.
Example: 34 bits
DR input value
Shows which bit pattern to shift into the data register in the Shift-DR state when this
instruction is active. Multiple such lines may exist, e.g. to distinguish between reads
and writes.
Example: aaaaaaar xxxxxxxx xxxxxxxx xxxxxxxx xx
DR output value
Shows the bit pattern shifted out of the data register in the Shift-DR state when this
instruction is active. Multiple such lines may exist, e.g. to distinguish between reads
and writes.
Example: xx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxeb
34.4.13.2
NEXUS_ACCESS
This instruction allows Nexus-compliant access to On-Chip Debug registers through the SAB.
OCD registers are addressed by their register index, as listed in the AVR32 Technical Reference
Manual. The 7-bit register index, a read/write control bit, and the 32-bit data is accessed through
the JTAG port.
The data register is alternately interpreted by the SAB as an address register and a data regis-
ter. The SAB starts in address mode after the NEXUS_ACCESS instruction is selected, and
toggles between address and data mode each time a data scan completes with the busy bit
cleared.
Starting in Run-Test/Idle, OCD registers are accessed in the following way:
1. Select the DR Scan path.
2. Scan in the 7-bit address for the OCD register and a direction bit (1=read, 0=write).
32072A–AVR32–03/09
912