AT32UC3A3256S_1 Datasheet, PDF (782/961 Pages) ATMEL Corporation – AVR32 32-Bit Microcontroller

AT32UC3A3
If the CDR register is not read before further incoming data is converted, the corresponding
Overrun Error bit in the SR register (SR.OVREn) is set.
In the same way, new data converted when DRDY is high sets the General Overrun Error bit in
the SR register (SR.GOVRE).
The OVREn and GOVRE bits are automatically cleared when the SR register is read.
Figure 29-3. GOVRE and OVREn Flag Behavior
TRIGGER
Read SR
CH0(CHSR)
CH1(CHSR)
LCDR
CRD0
CRD1
EOC0(SR)
Undefined Data
Data A
Undefined Data
Undefined Data
Conversion
Data B
Data A
Data B
Conversion
Data C
Data C
Read CDR0
EOC1(SR)
Conversion
Read CDR1
GOVRE(SR)
DRDY(ASR)
OVRE0(SR)
Warning: If the corresponding channel is disabled during a conversion or if it is disabled and
then reenabled during a conversion, its associated data and its corresponding EOC and OVRE
flags in SR are unpredictable.
32072A–AVR32–03/09
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