AT32UC3A3256S_1 Datasheet, PDF (642/961 Pages) ATMEL Corporation – AVR32 32-Bit Microcontroller

AT32UC3A3
•Detailed description
The data is written, following the next flow:
• When the bank is empty, TXINI and FIFOCON are set, what triggers an EPnINT interrupt if
TXINE is one.
• The user acknowledges the interrupt by clearing TXINI.
• The user writes the data into the current bank by using the USB Pipe/Endpoint nFIFO Data
(USBFIFOnDATA) register, until all the data frame is written or the bank is full (in which case
RWALL is cleared and the Byte Count (BYCT) field in UESTAn reaches the endpoint size).
• The user allows the controller to send the bank and switches to the next bank (if any) by
clearing FIFOCON.
If the endpoint uses several banks, the current one can be written while the previous one is
being read by the host. Then, when the user clears FIFOCON, the following bank may already
be free and TXINI is set immediately.
An “Abort” stage can be produced when a zero-length OUT packet is received during an IN
stage of a control or isochronous IN transaction. The Kill IN Bank (KILLBK) bit in UECONn is
used to kill the last written bank. The best way to manage this abort is to apply the algorithm rep-
resented on Figure 27-18 on page 642.
Figure 27-18. Abort Algorithm
Endpoint
Abort
TXINEC = 1
Disable the TXINI interrupt.
NBUSYBK _No
== 0?
Yes
EPRSTn = 1
KILLBKS = 1
Abort Done
KILLBK
Yes
== 1?
No
Abort is based on the fact
that no bank is busy, i.e.,
that nothing has to be sent
Kill the last written bank.
Wait for the end of the
procedure
27.7.2.13 Management of OUT endpoints
•Overview
OUT packets are sent by the host. All the data can be read which acknowledges or not the bank
when it is empty.
The endpoint must be configured first.
32072A–AVR32–03/09
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