AT32UC3A3256S_1 Datasheet, PDF (462/961 Pages) ATMEL Corporation – AVR32 32-Bit Microcontroller

AT32UC3A3
24.8.2.1
Clock Generation
The Clock Waveform Generator Register (CWGR) is used to control the waveform of the TWCK
clock. CWGR must be programmed so that the desired TWI bus timings are generated. CWGR
describes bus timings as a function of cycles of a prescaled clock. The clock prescaling can be
selected through the EXP field in CWGR.
f_prescaled
=
-------^f--^c--^l--^k--^p---^b-------
2^{(EXP + 1))}
CWGR has the following fields:
LOW: Prescaled clock cycles in clock low count. Used to time T_LOW. and T_BUF.
HIGH: Prescaled clock cycles in clock high count. Used to time T_HIGH.
STASTO: Prescaled clock cycles in clock high count. Used to time T_{HD_STA}, T_{SU_STA}, T_{SU_STO}.
DATA: Prescaled clock cycles for data setup and hold count. Used to time T_{HD_DAT}, T_{SU_DAT}.
EXP: Specifies the clock prescaler setting.
Note that the total clock low time generated is the sum of T_{HD_DAT} + T_{SU_DAT} + T_LOW.
Any slave or other bus master taking part in the transfer may extend the TWCK low period at any
time.
Figure 24-5. Bus Timing Diagram
t _LOW
t _HIGH
t _LOW
S
t _HD:STA
t
SU:DAT
t _HD:DAT
t _SU:DAT
t
SU:STO
P
t
SU:STA
Sr
24.8.2.2
Setting up and Performing a Transfer
Operation of TWIM is mainly controlled by the Control Register (CR) and the Command Register
(CMDR). The following list presents the main steps in a typical communication:
1. Before any transfers can be performed, bus timings must be configured by program-
ming the Clock Waveform Generator Register (CWGR). If operating in SMBus mode,
the SMBus Timing Register (SMBTR) register must also be configured.
2. If a DMA controller is to be used for the transfers, it must be set up.
3. CMDR or NCMDR must be programmed with a value describing the transfer to be
performed.
32072A–AVR32–03/09
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