AT32UC3A3256S_1 Datasheet, PDF (291/961 Pages) ATMEL Corporation – AVR32 32-Bit Microcontroller

AT32UC3A3
19.6.17 Performance Control Register
Name:
PCONTROL
Access Type:
Read/Write
Offset:
0x800
Reset Value:
0x00000000
31
30
29
28
27
26
25
24
-
-
MON1CH
23
22
21
20
19
18
17
16
-
-
MON0CH
15
14
13
12
11
10
9
8
-
-
-
-
-
-
CH1RES
CH0RES
7
6
5
4
3
2
1
0
-
-
CH1OF
CH0OF
-
-
CH1EN
CH0EN
• MON1CH: PDCA Channel to Monitor with Counter 1
• MON0CH: PDCA Channel to Monitor with Counter 0
Due to performance monitor hardware resource sharing, the two monitor channels should NOT be programmed to monitor the
same PDCA channel. This may result in UNDEFINED performance monitor behavior.
• CH1RES: Channel 1 Counter Reset
Writing a one to this bit will reset the counter in the channel 1.
Writing a zero to this bit has no effect.
Always read as 0.
• CH0RES: Channel 0 Counter Reset
Writing a one to this bit will reset the counter in the channel 0.
Writing a zero to this bit has no effect.
Always read as 0.
• CH1OF: Channel Overflow Freeze
1: All channel registers are frozen just before DATA or STALL overflows.
0: The channel registers are reset if DATA or STALL overflows.
• CH1OF: Channel Overflow Freeze
1: All channel registers are frozen just before DATA or STALL overflows.
0: The channel registers are reset if DATA or STALL overflows.
• CH1EN: Channel 1 Enable
1: Channel 1 is enabled.
0: Channel 1 is disabled.
• CH0EN: Channel 0 Enable
1: Channel 0 is enabled.
0: Channel 0 is disabled.
32072A–AVR32–03/09
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