AT91SAM9RL64_14 Datasheet, PDF (848/903 Pages) ATMEL Corporation – Multi-layer AHB Bus Matrix for Large Bandwidth Transfers

AT91SAM9R64/RL64
43.10.10 TSADCC Last Converted Data Register
Register Name:
TSADCC_LCDR
Access Type:
Read-only
31
30
29
28
27
26
25
24
–
–
–
–
–
–
–
–
23
22
21
20
19
18
17
16
–
–
–
–
–
–
–
–
15
14
13
12
11
10
–
–
–
–
–
–
9
8
LDATA
7
6
5
4
3
2
1
0
LDATA
• LDATA: Last Data Converted
The analog-to-digital conversion data is placed into this register at the end of a conversion on any analog channel and
remains until a new conversion on any analog channel is completed.
43.10.11 TSADCC Interrupt Enable Register
Register Name:
TSADCC_IER
Access Type:
Write-only
31
30
29
28
–
–
–
–
23
22
21
20
–
–
NOCNT
PENCNT
15
14
13
12
–
–
OVRE5
OVRE4
7
6
5
4
–
–
EOC5
EOC4
• EOCx: End of Conversion Interrupt Enable x
• OVREx: Overrun Error Interrupt Enable x
• DRDY: Data Ready Interrupt Enable
• GOVRE: General Overrun Error Interrupt Enable
• ENDRX: End of Receive Buffer Interrupt Enable
• RXBUFF: Receive Buffer Full Interrupt Enable
• PENCNT: Pen Contact
• NOCNT: No Contact
0 = No effect.
1 = Enables the corresponding interrupt.
27
–
19
RXBUFF
11
OVRE3
3
EOC3
26
–
18
ENDRX
10
OVRE2
2
EOC2
25
–
17
GOVRE
9
OVRE1
1
EOC1
24
–
16
DRDY
8
OVRE0
0
EOC0
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