AT91SAM9RL64_14 Datasheet, PDF (35/903 Pages) ATMEL Corporation – Multi-layer AHB Bus Matrix for Large Bandwidth Transfers

AT91SAM9R64/RL64
10.2
Peripheral Identifiers
The Table 10-1 defines the Peripheral Identifiers of the AT91SAM9R64/RL64. A peripheral iden-
tifier is required for the control of the peripheral interrupt with the Advanced Interrupt Controller
and for the control of the peripheral clock with the Power Management Controller.
Table 10-1. AT91SAM9R64/RL64 Peripheral Identifiers
Peripheral ID
Peripheral Mnemonic Peripheral Name
0
AIC
Advanced Interrupt Controller
1
SYSC
System Controller Interrupt
2
PIOA
Parallel I/O Controller A,
3
PIOB
Parallel I/O Controller B
4
PIOC
Parallel I/O Controller C
5
PIOD
Parallel I/O Controller D
6
US0
USART 0
7
US1
USART 1
8
US2
USART 2
9
US3
USART 3
10
MCI
Multimedia Card Interface
11
TWI0
Two-Wire Interface 0
12
TWI1
Two-Wire Interface 1
13
SPI
Serial Peripheral Interface
14
SSC0
Synchronous Serial Controller 0
15
SSC1
Synchronous Serial Controller 1
16
TC0
Timer Counter 0
17
TC1
Timer Counter 1
18
TC2
Timer Counter 2
19
PWMC
Pulse Width Modulation Controller
20
TSADCC
Touch Screen ADC Controller
21
DMAC
DMA Controller
22
UDPHS
USB Device High Speed
23
LCDC
LCD Controller (AT91SAM9RL64 only)
24
AC97
AC97 Controller
25-30
-
Reserved
31
AIC
Advanced Interrupt Controller
External Interrupt
FIQ
IRQ
Note: Setting AIC, SYSIRQ, LCDC and IRQ bits in the clock set/clear registers of the PMC has no effect.
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6289D–ATARM–3-Oct-11