AT91SAM9RL64_14 Datasheet, PDF (83/903 Pages) ATMEL Corporation – Multi-layer AHB Bus Matrix for Large Bandwidth Transfers

AT91SAM9R64/RL64
Before performing the jump to the application in internal SRAM, all the PIOs and peripherals
used in the boot program are set to their reset state.
Table 14-5. Pins Driven during Boot Program Execution
Peripheral
Pin
MCI
MCDA0
MCI
MCCDA
MCI
MCCK
MCI
MCDA1
MCI
MCDA2
MCI
MCDA3
SPI
MISO
SPI
MOSI
SPI
SPCK
SPI
NPCS0
PIO Controller B
NAND OE
PIO Controller B
NAND WE
PIO Controller B
NANDCS
Address Bus
NAND ALE
Address Bus
NAND CLE
DBGU
DRXD
DBGU
DTXD
PIO Line
PIOA0
PIOA1
PIOA2
PIOA3
PIOA4
PIOA5
PIOA25
PIOA26
PIOA27
PIOA28
PIOB4
PIOB5
PIOB6
A21
A22
PIOA21
PIOA22
83
6289D–ATARM–3-Oct-11