AT91SAM9RL64_14 Datasheet, PDF (57/903 Pages) ATMEL Corporation – Multi-layer AHB Bus Matrix for Large Bandwidth Transfers

AT91SAM9R64/RL64
12.3.9
New ARM Instruction Set
.
Table 12-3.
Mnemonic
BXJ
New ARM Instruction Mnemonic List
Operation
Mnemonic
Branch and exchange to
Java
MRRC
BLX ⁽¹⁾
Branch, Link and exchange
MCR2
SMLAxy
SMLAL
SMLAWy
Signed Multiply Accumulate
16 * 16 bit
Signed Multiply Accumulate
Long
Signed Multiply Accumulate
32 * 16 bit
MCRR
CDP2
BKPT
SMULxy
Signed Multiply 16 * 16 bit
PLD
SMULWy Signed Multiply 32 * 16 bit
STRD
QADD
Saturated Add
STC2
QDADD
Saturated Add with Double
LDRD
QSUB
Saturated subtract
LDC2
QDSUB
Saturated Subtract with
double
CLZ
Operation
Move double from
coprocessor
Alternative move of ARM reg
to coprocessor
Move double to coprocessor
Alternative Coprocessor
Data Processing
Breakpoint
Soft Preload, Memory
prepare to load from address
Store Double
Alternative Store from
Coprocessor
Load Double
Alternative Load to
Coprocessor
Count Leading Zeroes
Notes: 1. A Thumb BLX contains two consecutive Thumb instructions, and takes four cycles.
12.3.10 Thumb Instruction Set Overview
The Thumb instruction set is a re-encoded subset of the ARM instruction set.
The Thumb instruction set is divided into:
• Branch instructions
• Data processing instructions
• Load and Store instructions
• Load and Store multiple instructions
• Exception-generating instruction
Table 5 shows the Thumb instruction set. Table 12-4 gives the Thumb instruction mnemonic list.
Table 12-4.
Mnemonic
MOV
ADD
SUB
CMP
TST
AND
Thumb Instruction Mnemonic List
Operation
Mnemonic
Move
MVN
Add
ADC
Subtract
SBC
Compare
CMN
Test
NEG
Logical AND
BIC
Operation
Move Not
Add with Carry
Subtract with Carry
Compare Negated
Negate
Bit Clear
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6289D–ATARM–3-Oct-11