AT91SAM9RL64_14 Datasheet, PDF (590/903 Pages) ATMEL Corporation – Multi-layer AHB Bus Matrix for Large Bandwidth Transfers

AT91SAM9R64/RL64
Figure 37-13. DMAC Transfer Replay Mode is Enabled for the Source and Contiguous Destination Address
Channel Enabled by
software
Buffer Transfer
Replay mode for SADDRx,
Contiguous mode for DADDRx
CTRLAx, CTRLBx
Buffer Complete interrupt
generated here
Buffer Transfer Complete
interrupt generated here
yes
Is HDMA in Row1of
HDMA State Machine Table?
Channel Disabled by
hardware
no
no
DMA_EBCIMR[x]=1?
yes
Stall until STALLED field is
cleared by software writing
KEEPON Field
37.3.4.7
Multi-buffer DMAC Transfer with Linked List for Source and Contiguous Destination Address (Row 2)
1. Read the Channel Enable register to choose a free (disabled) channel.
2. Set up the linked list in memory. Write the control information in the
LLI.DMAC_CTRLAx and LLI.DMAC_CTRLBx register location of the buffer descriptor
for each LLI in memory for channel x. For example, in the register, you can program the
following:
c. Set up the transfer characteristics, such as:
– i. Transfer width for the source in the SRC_WIDTH field.
– ii. Transfer width for the destination in the DST_WIDTH field.
– iii. Source AHB master interface layer in the SIF field where source resides.
– iv. Destination AHB master interface layer in the DIF field where destination resides.
– v. Incrementing/decrementing or fixed address for source in SRC_INCR field.
– vi. Incrementing/decrementing or fixed address for destination DST_INCR field.
6289D–ATARM–3-Oct-11
590