AT91SAM9RL64_14 Datasheet, PDF (206/903 Pages) ATMEL Corporation – Multi-layer AHB Bus Matrix for Large Bandwidth Transfers

23.3 Application Example
23.3.1
Software Interface
The SDRAM address space is organized into banks, rows, and columns. The SDRAM controller
allows mapping different memory types according to the values set in the SDRAMC configura-
tion register.
The SDRAM Controller’s function is to make the SDRAM device access protocol transparent to
the user. Table 23-2 to Table 23-7 illustrate the SDRAM device memory mapping seen by the
user in correlation with the device structure. Various configurations are illustrated.
23.3.2 32-bit Memory Data Bus Width
Table 23-2. SDRAM Configuration Mapping: 2K Rows, 256/512/1024/2048 Columns
CPU Address Line
27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bk[1:0]
Row[10:0]
Column[7:0]
M[1:0]
Bk[1:0]
Row[10:0]
Column[8:0]
M[1:0]
Bk[1:0]
Row[10:0]
Column[9:0]
M[1:0]
Bk[1:0]
Row[10:0]
Column[10:0]
M[1:0]
Table 23-3. SDRAM Configuration Mapping: 4K Rows, 256/512/1024/2048 Columns
CPU Address Line
27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bk[1:0]
Row[11:0]
Column[7:0]
M[1:0]
Bk[1:0]
Row[11:0]
Column[8:0]
M[1:0]
Bk[1:0]
Row[11:0]
Column[9:0]
M[1:0]
Bk[1:0]
Row[11:0]
Column[10:0]
M[1:0]
Table 23-4. SDRAM Configuration Mapping: 8K Rows, 256/512/1024/2048 Columns
CPU Address Line
27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bk[1:0]
Row[12:0]
Column[7:0]
M[1:0]
Bk[1:0]
Row[12:0]
Column[8:0]
M[1:0]
Bk[1:0]
Row[12:0]
Column[9:0]
M[1:0]
Bk[1:0]
Row[12:0]
Column[10:0]
M[1:0]
Notes: 1. M[1:0] is the byte address inside a 32-bit word.
2. Bk[1] = BA1, Bk[0] = BA0.
206 AT91SAM9R64/RL64
6289D–ATARM–3-Oct-11