AT697E_09 Datasheet, PDF (70/154 Pages) ATMEL Corporation – Rad-Hard 32 bit SPARC V8 Processor

AT697
Figure 39. DSU Communication Link Block Diagram
DSURX
Baud-rate
generator
8*bitclk
Serial port
Controller
Receiver shift register
Transmitter shift register
AMBA APB
DSUTX
Data Frame
AHB master interface
AHB data/response
AMBA AHB
A simple communication protocol is supported to transmit access parameters and data.
A link command consist of a control byte, followed by a 32-bit address, followed by
optional write data. If the LR bit in the DSU control register is set, a response byte will be
sent after each AHB transfer. If the LR bit is not set, a write access does not return any
response, while a read access only returns the read data.
Data is sent on 8-bit basis.
Figure 40. DSU UART Data Frame
Start D0 D1 D2 D3 D4 D5 D6 D7 Stop
Commands
Through the communication link, a read or write transfer can be generated to any
address on the internal bus. A response byte is can optionally be sent when the proces-
sor goes from execution mode to debug mode. Block transfers can be performed be
setting the length field to n-1, where n denotes the number of transferred words. For
write accesses, the control byte and address is sent once, followed by the number of
data words to be written. The address is automatically incremented after each data
word. For read accesses, the control byte and address is sent once and the correspond-
ing number of data words is returned.
Figure 41. DSU Commands
DSU Write Command
Send 11 Length -1 Addr[31:24] Addr[23:16] Addr[15:8] Addr[7:0] Data[31:24] Data[23:16] Data[15:8] Data[7:0]
Receive
Resp. byte (optional)
DSU Read command
Send 10 Length -1 Addr[31:24] Addr[23:16] Addr[15:8]
Addr[7:0]
Receive _{Data[31:24] Data[23:16] Data[15:8] Data[7:0]}
Resp. byte (optional)
Response byte encoding
bit 7:3 = 000000
bit 2 = DMODE
bit 1:0 = HRESP
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