AT697E_09 Datasheet, PDF (47/154 Pages) ATMEL Corporation – Rad-Hard 32 bit SPARC V8 Processor

Watchdog
Figure 31. Timer/Counter 1/2 Block Diagram
Reload Reg.
TIMRn
load
Control Reg.
TIMCTRn
Control Logic
timer interrupts
(irq 8 & 9)
count tick
Counter Reg.
TIMCn
enable/disable
=0xFFFFFF
The watchdog operates the same way as the timers, with the difference that it is always
enabled and upon underflow asserts the external signal WDOG. This signal can be used
to generate a system reset.
If the watchdog counter is refreshed by writing to WDG register before the counter reaches zero,
the counter restarts counting from the new value.
If the counter is not refreshed before the counter reaches zero, WDOG signal is asserted.
After reset, the watchdog is automatically enabled and starts running.
Note: Reading wdc field of the watchdog register gives the loading (or re-loading) value, not
the effective count value.
Figure 32. Watchdog Block Diagram
Watchdog Reg.
TIMRn
Control Logic
clock
WDOG
=0xFFFFFF
46 AT697E
4226G–AERO–05/09