AT697E_09 Datasheet, PDF (15/154 Pages) ATMEL Corporation – Rad-Hard 32 bit SPARC V8 Processor

AT697
Program Counters
ALU - Arithmetic Logic Unit
Register File - Windows
• Write: The result of any ALU, logical, shift, or cache read operations re written back
to the register file.
All five stages operate in parallel, working on up to five different instructions at a time. A
basic ’single-cycle’ instruction enters the pipeline and completes in five cycles.
By the time it reaches the write stage, four more instructions have entered and are driv-
ing through the pipeline behind it. So, after the first five cycles, a single-cycle instruction
exits the pipeline and a single-cycle instruction enters the pipeline on every cycle. Of
course, a ’single-cycle’ instruction actually takes five cycles to complete, but they are
called single cycle because with this type of instruction the processor can complete one
instruction per cycle after the initial five-cycle delay.
In order to maximize performance and parallelism, the AT697 SPARC implementation uses
powerful AMBA bus. Instructions in the program memory are executed with a five level pipelin-
ing. While one instruction is being executed, the next instruction is pre-fetched from the program
memory. This concept enables instructions to be executed in every clock cycle.
Two 32-bit program counters (PC and nPC) are provided. The 32-bit PC contains the
address of the instruction currently being executed by the IU. The nPC holds the
address of the next instruction to be executed (assuming a trap does not occur).
When a trap occurs, the PC address is saved in the local register (l1) while the nPC
address is saved in the local register (l2). When returning from trap, l1 value is copied
back to PC and l2 value is copied back to nPC.
The high-performance ALU operates in direct connection with all the 32 general purpose
working registers. Within a single clock cycle, arithmetic operations between general
purpose registers or between a register and an immediate memory address are exe-
cuted. The implementation of the architecture also provide a powerful multiplier/divider
supporting both signed and unsigned multiplication/division.
Support for high performance 64-bit operation is also provided.The 32-bit Y register con-
tains the most significant word of the double-precision product of an integer
multiplication, as a result of either an integer multiply instruction, or of a routine that uses
the integer multiply step instruction. The Y register also holds the most significant word
of the double-precision dividend for an integer divide instruction.
The fast access register file contains 8 SPARC register windows. Each window consists
in a 32-register set. When a program is running, it has access to 32 32-bit processor
registers which include 8 global registers plus 24 registers that belong to the current reg-
ister window.
• The first 8 registers in the window are called the in registers’ (i0-i7). When a function
is called, these registers may contain arguments that can be used.
• The next 8 are the ’local registers’ (l0-l7) which are scratch registers that can be
used for anything while the function executes.
• The last 8 registers are the ’out registers’ (o0-o7) which the function uses to pass
arguments to functions that it calls.
AT697 register file implementation is based on two dual-port rams. The first dual-port
ram corresponds to %rs1 operand of a SPARC instruction while the second corre-
sponds to %rs2 operand. The two dual-port rams contents are always equal.
When one function calls another, the calling function can choose to execute a SAVE
instruction. This instruction decrements an internal counter, the current window pointer
(cwp), shifting the register window downward. The caller’s out registers then become
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